ADuC7022 - 13 GPIOs or 15?

When I look at the current data sheet, it says in the selection table that the 7022 only has 13 GPIOs. But I count 16 on the pin out drawing and in the pin list. Any idea why they say there are only 13? Is there some restriction on three of these pins that they can't count them as GPIO? I see that one is a JTAG TRST, one is a BM (boot mode) at power up time and one is a MRST output. These are the only functions I can see that might disqualify an IO as being considered "available", but I the way they are described in the data sheet I expect all of these will work just fine as GPIO. Is this why they count 13 and I count 16?

1 P0.0 2 P0.3 3 P0.4 4 P0.5 5 P0.6 6 P0.7 7 P1.0 8 P1.1 9 P1.2 10 P1.3 11 P1.4 12 P1.5 13 P1.6 14 P1.7 15 P2.0 16 P4.2

Unfortunately, I'm not sure even 16 will be enough IOs. They sure seem to burn up a lot of pins on a 40 pin package. 10 are hard dedicated to the ADC/DAC functions, 4 for JTAG and 10 more for power, reset and clock. I guess they wanted to maintain separate IOs for the analog functions to optimize the performance of the ADC/DACs... that is what is supposed to set these chips apart from the other ARM MCUs. :^)

Reply to
rickman
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rickman wrote: .2

Yes multiplexing discrete I/O with A/D inputs pins degrades the accuracy of the A/D. I have seen chips specify different A/D accuracies on different pins depending on how much and what was multiplexed on that pin.

However, you still can use (and I have) A/D inputs as general purpose discrete inputs (if the reading in above, say, 1.8 volts the discrete is high, below it is a zero). Same concept with DAC's as a general purpose discrete outputs. The 7022 has a fast 1 Mhz A/D so it isn't so bad, time wise, to do this, it's just a couple if statements for each discrete.

steve

Reply to
steve

Yes, I know. But it is hard to do fast work with ADC inputs and I really need outputs and bidirs. I need about 17 I/Os to implement a parallel port to boot an FPGA from a NAND flash. I have not done the exact pin count, but it will need an 8 bit bidir data bus, about 5 outputs for the NAND control lines and perhaps another 4 or 5 to control the FPGA. Unless I can think of a simpler way to do this I'll look for a processor with more I/Os and still under $5. The Atmel parts are pretty good and I think are lower power. But they don't have the 125C temperature range of the ADuC parts, so I have to add a $1.50 temperature part to shut down the board when out of temperature range. Still that is cheaper than the ADuC7025.

Reply to
rickman

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