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ADC Question on 'F2812

Hi:

The TMS320F2812 Analog to Digital Converter (ADC) Peripheral Reference Guide (SPRU060) states on page 2-12 that: "After each conversion ... in a conversion sequence, the pointer increases by 1."

This is referring to the SEQnPTR bit fields in the AUTO_SEQ_SR register, which maintain the current states of the two 8-state ADC conversion sequencers.

However, my program experiments seem to indicate that this register instead maintains the value of the last conversion state, rather than incrementing to point to the next as the documentation says. That would imply that it increments instead upon start-of-conversion, rather than after.

I have discovered this by configuring the SEQ1 to operate in start-stop mode. That is, I set MAXCONV1 to have a value of 0 so that only one conversion would be performed. I also configured the ADC, PIE, and CPU to generate an interrupt at the end of a conversion sequence. I set the ADCTRL1:CONTRUN bit to zero.

Sure enough, when I get to my interrupt service routine, I find that the SEQ1PTR value is zero after the first conversion (whose result is in RESULT0, the SEQ1PTR value is 1 after the second conversion (whose result is in RESULT1), etc.

If I set MAXCONV1 to perform a multiple conversion sequence before interrupting, then the same behavior is observed. So if I set MAXCONV1=7 to generate a full 8 conversions, I get SEQ1PTR=7 when the ISR is reached.

This is definitely inconsistent with the documentation.

Has anyone else noticed this?

Thanks for input.

Good day!

--
_______________________________________________________________________
Christopher R. Carlen
Principal Laser/Optical Technologist
Sandia National Laboratories CA USA
crcarle@sandia.gov -- NOTE: Remove "BOGUS" from email address to reply.
Reply to
Chris Carlen
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Chris,

I've worked with the 2812, but never worked with the pointer registers for the ADC. Just read them directly with my own pointer, after the conversion sequence was complete.

Check the Errata, TI is very good in documenting its problems. Also check the TI discussion forums.

BTW, is the ADC still only 9 bit accurate? What silicon do you have?

Cheers

Reply to
Martin Riddle

ADC. Just read them directly with my own pointer,

Hi, thanks for the reply.

I'm implementing a 4-phase sampling technique, so must examine the sequencer state in the ADC interrupt to figure out which channel was just converted which triggered the interrupt. This is in contrast to a scheme where you convert a group of channels, then interrupt which sounds like what you have done.

I am fairly confident in the behavior that I am observing, just would like to have it acknowledged by TI. So...

Yes, I will be checking this out. Let's see if I can find the errata...

Ugh. I've never seen so many manuals for a single part.

Ack! Wouldn't you know it. Ti says in the Errata: "SEQ2 STATE2-0 and SEQ1 STATE3-0 bit fields...are the pointers of SEQ2 and SEQ1 respectively. These bits are reserved for TI testing and should not be used in customer applications. Workaround: none."

Blah! I will have to contact them about this. It seems silly. They are doing what I want them to do, just off by a count of 1 from what the manual says, which says nothing about them being reserved. (Pays to read the errata early on, I suppose).

The real trouble is that I can't possibly implement the 4-phase sampling technique as efficiently as I'd like unless I read these bits. Otherwise, I will have to maintain my own counter in the ISR, and waste CPU time on that.

I have rev. C on the eZdsp board, and rev. E F2810 chips in my drawer. My F2812's are on backorder. Apparently the ADC accuracy problems were on the TMX silicon, and aren't in the production or "C" chips.

Trouble is with the evaluation board, it is impossible to get low noise signal into the ADC. The board broadcasts quite a bit. With 7mV RMS noise at the ADC input, I can't even get the 8th MSB to stay still. So I've got a lowsy 7 bits.

Hmm. Maybe I should just plan to integrate my own 12-bit A/D onto a prototype board.

Good day!

--
_______________________________________________________________________
Christopher R. Carlen
Principal Laser/Optical Technologist
Sandia National Laboratories CA USA
crcarle@sandia.gov -- NOTE: Remove "BOGUS" from email address to reply.
Reply to
Chris Carlen

Glad I could help.

You might want to look at the ADC's TI has. I never got a chance to use it. Designed for motor control, it has 6 S/H at 16 bits(14bit), ADS8364. Might be worth a look if 4us is fast enough.

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Cheers

the ADC. Just read them directly with my own pointer,

Reply to
Martin Riddle

Designed for motor control, it has 6 S/H at 16

Thanks for the tip. That's an interesting converter. I think I need 8 channels though (not conventional 3p motor drive).

I'm looking at TI's ADS7852, and Linear's LTC1851/3 and LTC1863/7.

Hard to decide what interfaces to prefer. I need a pair of 4 channel DACs, so to put everything on the XINTF, or use the SPI for the A/D and McBSP in SPI mode for the D/A (or vice versa) are the apparent choices.

Interfacing to the CPU bus seems a bit more formidable since I've never done that before, but maybe it's no more difficult than getting two serial interfaces working. Might only need one serial interface for all converter chips anyway. Not sure yet.

Good day!

--
_______________________________________________________________________
Christopher R. Carlen
Principal Laser/Optical Technologist
Sandia National Laboratories CA USA
crcarle@sandia.gov -- NOTE: Remove "BOGUS" from email address to reply.
Reply to
Chris Carlen

ADC. Just read them directly with my own pointer,

We where having problems getting rid of the ADC noise. Running directly from a switching regulator was one cause. The DSP has a large dynamic current consumption that couldn't be followed by the switcing regulator. Adding many caps (extremely low ESR, high capacitance) didn't improve anything. Using a linear regulator did help a lot. I think current performance is a little bit better than 10 bits.

In the preliminary datasheet TI promised an ENOB of 10.4 bits, now it is specified at 10.1 bits. Don't follow the recommendation to split ground planes for analog and digital. Use one plane and smart sectioning of analog and digital circuitry on the pcb. Makes a big difference in generated EMI.

Reinier

Reply to
Reinier

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