I use Cypress EZ-USB FX2 for a data transmit system, FX2 in Slave FIFO mode, with FPGA as the master. I write proogram to transmit data from the PC to FX2.(direc is OUT) The problem is , when I set IFCONFIG = 0xC3 in firmware, which means Slave FIFOs executes on internal 48MHz clk source, it works well. but I need to set IFCONFIG = 0x43, which means Slave FIFOs executes on external clk source provied by FPGA through IFCLK pin, in this case, I can not write data into FX2. why ? 6MHz clock already sent to the IFCLK pin.
Bad luck on entering a nightmare world. For example, you need a clock running to initialise Port D so your clock must be up. Because the FX2 chip can be running (powered from the USB bus) before our hardware was running (as indicated by HuskyIsReady), we had to be careful about when to initialise things. FWIW, I ended up with the following messy code:
#define HUSKY_IS_READY ((IOE & 4) ? 1 : 0)
... // // We need Port E to see if Husky is ready. // PORTECFG = 0; // no alternate signals IFCONFIG &= ~bmGSTATE; // GSTATE is false so it does not relay GPIF signals to Port E OEE = ((1
An earlier post "welcome to a nightmare world" just about sums it up with the cypresss FX2 well-known weakness in monitoring capability which reduces us to "debug by LED flashing".
In our case we wanted to use port D as output port pins and not as FD15-8. So we followed the instructions to set all WORDWIDE=0 in the EPxFIFOCFG and got no output on port D!
The solution was to ensure that the IFCLK input to the slave fifos was actually driven from the internal source, at least for a cycle. In our system, it is driven from a CPLD which is in turn clocked from CLKOUT. But if the CPLD is not programmed yet (e.g. during firmware development) it doesn't provide IFCLK. This is enough to prevent port D from becoming GPIO.
Also FWIW, here is our TD_Init
void TD_Init(void) // Called once at startup { // set the CPU clock to 48MHz //CPUCS = ((CPUCS & ~bmCLKSPD) | bmCLKSPD1) ; CPUCS = 0x12 ; // 1_0010 : CLKSP1:0=10, cpu clockspeed 48MHz, drive CLKOUT output pin 100 which clocks CPLD
/* (from raphael berner: the clocking is as follows: the fx2 clockes the CPLD by the CLKOUT pin (pin 100), and the CPLD clocks the fifointerface on IFCLK, so in the firmware you should select external clocksource in the FX2 for the slave FIFO clock source.
*/
IOC = 0x00; IOA = 0x00; IOE= 0x00; // set port output default values - enable them as outputs next
//set FIFO flag configuration: FlagB: EP6 full, flagC and D unused SYNCDELAY; PINFLAGSAB = 0xE8; // 1110_1000 SYNCDELAY;
cycleCounter=0; // missedEvents=0xFFFFFFFF; // one interrupt is generated at startup, maybe some cpld registers start in high state
LED=1; // turn on LED
clock=1; bitIn=0; latch=1; powerDown=0; // init biasgen ports and pins EZUSB_InitI2C(); // init I2C to enable EEPROM read and write
initDAC();
JTAGinit=TRUE;
IT0=1; // make INT0# edge-sensitive EX0=0; // do not enable INT0#
IT1=1; // INT1# edge-sensitve EX1=0; // do not enable INT1#
// timer2 init for scanner clocking in continuous mode T2CON=0x00; // 0000 0100 timer2 control, set to 16 bit with autoreload, timer stopped
RCAP2L=0x00; // timer 2 low register loaded from vendor request. RCAP2H=0xFF; // starting reload values, counter counts up to 0xFFFF from these and generates interrupt when count rolls to 0
ET2=0; // disable interrupt to start
toggleVReset();
// now switch to external IFCLK for FIFOs SYNCDELAY; // may not be needed IFCONFIG = 0x23; // 0010_0011 // extenal clock, slave fifo mode SYNCDELAY; // may not be needed
ElectronDepot website is not affiliated with any of the manufacturers or service providers discussed here.
All logos and trade names are the property of their respective owners.