A new benchmark suitable for small systems: stdcbench

mar?i, 20 februarie 2018, 21:58:12 UTC+2, Philipp Klaus Krause a scris :

Is it 12clk/instruction or something? In this case 48MHz is misleading. Same for PICs which are 4clks/instr. Microchip usually give another number, the Mips, for example 64MHz/16Mips.

So the Cypress chips is 48MHz/4Mips maybe?

When I worked with 12clks/instr 8051 I always talked about it as 1Mips cpu.

Speaking of that, we always take the newlib/nelib-nano/whatever-lib for gra nted. An interesting possibility would be to compile the same lib bench without l ib calls (of course, another version of the program doing the exact same thing but w ith no lib calls) Just to see how we stand. It would be quite a good indicator of the performance of the lib.

Am 21.02.2018 um 08:37 schrieb snipped-for-privacy@gmail.com:

The Cypress EZ-USB can execute most 1-byte instructions in 4 clock cycles. Most 2-byte instructions take 8 clock cycles. Branch instructions tend to take 16 clock cycles. A few instrcutions take even longer.

I gave the 48 Mhz figure mostly for reproduction of results (though the port can be found in the examples for stdcbench now anyway).

Philipp

It is common for modern 8051 implementations to have 4 oscillator clocks per instruction clocks. The original 8051 had 12 oscillator clocks per instruction clock.

Most single byte register-to-register operations take 1 instruction clock. Memory access adds to that, as do multi-byte instructions, jumps, calls, etc.

Am 20.02.2018 um 17:30 schrieb Philipp Klaus Krause:

Flash wait cycles indeed make a big difference with the STM32s: At stdcbench 0.4, the STM32F103 (Cortex-M3) at 36 Mhz with prefetch buffer enabled gets 22% higher scores with 1 wait state vs. 2 wait states.

Philipp