8255 chip mode 2 question

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I have a 8051 development board with an 8255 chip for port expansion.
I have a device which I need to hook up to this 8255 chip.  The device
has very simple interface:

Ad0, Ad1, Ad2, Ad3    ======> address bus
D0, D1, D2, D3, D4, D5, D6, D7 ====> data bus

I am thinking of the following arrangement:

device         8255 port             8255 mode
------         ---------             ---------

Ad0   <-------  C0                    Mode 0
Ad1   <-------  C1                  (C0-C3 in output)
Ad2   <-------  C2
Ad3   <-------  C3

D0   <------->  A0                    Mode 2
D1   <------->  A1                 (A0-A3 in bidirectional for r/w)
D2   <------->  A2
D3   <------->  A3
D4   <------->  A4
D5   <------->  A5
D6   <------->  A6
D7   <------->  A7

I will program the 8255 with the mode 0 & mode 2 combination.
The question is, knowing that pin C3 is used in Mode 2 of 8255 as an
INTRA pin, will I be able to write the proper 4-bit address to Ad0-Ad3
through C0-C3?  I read the datasheet but that didn't clarify for me.

Of course, simple solution would be to use mode 0 but I want to use
mode 2 so I won't have to switch directions of the data port each time
I flip from reading to writing and vice versa.

Thanks for any help.


Re: 8255 chip mode 2 question
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    if you are changing modes with the 8255 be very careful. It appears to
have a feature whereby the values written to output ports are lost/changed
when the mode register is written to.

You appear to be describing (but I could be wrong) using one of the ports as
I/O and changing modes of the 8255 to switch the port from input to output
mode and vice-versa. I tried this technique but ran into a known "feature" of
this device.

It is a long time since I used this part and suffered from this problem. I
have more reecntly seen this issue raised in various newsrgoups. I suggest
doing a search to confirm and correct my first paragraph (or perhaps someone
can post a more accurate summary of this feature).



Re: 8255 chip mode 2 question

I think I did not make myself clear.  I am trying to avoid mode
switches.  The 8255 datasheet says that you are allowed to have a
combination of modes for Group A and Group B ports.  What I want to do
is set port A to mode 2 so it is bidirectional.  That would allow me
to read/write data to the data bus without doing a switch each time.
So I will set Group A (port A and high nibble of port C [bits C4-C7])
to mode 2.  That leaves Group B which is the low nibble of port C
[bits C0-C3] and all of port B.  I will set group B to mode 0 with the
port C nibbles in output mode.  So far, so good.  The issue I would
like help in elucidating is that I need a 4-bit address bus for which
I will be using port C (C0-C3) in output mode, like this:

device         8255 port             8255 mode
------         ---------             ---------

Ad0   <-------  C0                    Mode 0
Ad1   <-------  C1                  (C0-C3 in output)
Ad2   <-------  C2
Ad3   <-------  C3

However, the 8255 datasheet says that in mode 2, bits C0, C1, C2 are
I/O while C3 is redefined as INTRA.  So when I assert the address on
port C, I know the C0, C1, and C2 bits will be fine but what about bit
C3?  Will I be able to output the full 4-bit address on C0-C3 or only
C0-C2 will work leaving out C3?  I am confused about whether I could
output to bit C3 because it falls as part of Group B but is redefined
for Group A's use when Group A set to mode 2.

Put simply, I want to know if I can output the address on either
nibbles of port C (I don't care which nibble) with port A in
bidirectional mode.

I hope I am getting across....any help from experienced people would
be appreciated....



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Re: 8255 chip mode 2 question
I did some more research and it seems that to implement the
bidirectional data transfer (mode 2), one has to implement the control
signals also on port C.  Does anyone know if this is correct?  I was
assuming that one can simply write and read to/from port A without
using these signals.


Re: 8255 chip mode 2 question

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Sorry James, but it won't work the way you want.  When Port A is set to Mode
2, 5 bits of Port C (Pc3-Pc7) are set for control/status of Port A, leaving
only 3 bits of Port C for the address output you intend.  There's no way
around this, just as you've seen in the data sheets.

You CAN, however, use all 8 bits of Port B (or only 4 bits, if you wish) to
output the 4-bit address information to your device.

The 8255 in Bi-Directional I/O is rather cumbersome.  It's further
complicated by having to use the port in a 'strobed' configuration.  In
other words, writing data to Port A for output will not actually output the
data until the /AckA signal (Pc6) is strobed LOW.  Also, when using Port A
for input, the data will not be latched into Port A until the /StbA signal
(Pc4) is strobed LOW.  In other words, you'll need to implement at least
these two control signals in your 'simple' interface.

It seems as though you're looking for a 'transparent' I/O solution.  Only
Mode 0 operates that way; both Mode 1 and Mode 2 are 'strobed' (meaning
control signals are necessary to actually effect the I/O operation.)


Re: 8255 chip mode 2 question
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You just refreshed an OLD (over 20 years ago) memory.

As I recall, yes, to do bidirectional (mode 2) on an 8255, you have to do the
control signals on port C.

Re: 8255 chip mode 2 question
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Please check the handshake sequences carefully - the 8255 handshakes are
not completely compliant with the usual two-wire handshakes.

And - yes - the port C is pretty completely reserved in bidirectional mode.

Brings memories since years - the 8255A is pretty stubborn chip to
converse with. You might be better off with a couple of three-state
buffers and latches and doing the handshakes with software.


Tauno Voipio
tauno voipio @ iki fi

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