68705U/R , misc register function

In the 68HC05 this is

SERIAL PERIPHERAL CONTROL REGISTER (SPCR) In most systems, this register is written only once shortly after reset to initialize the SPI system. Bit 7 SPIE reset 0 SPI interrupt enable 6 SPE 0 SPI system enable 4 MSTR 0 Master (1) or slave (0) mode select 3 CPOL 0 Clock polarity: 0 active-high, 1:active low 2 CPHA 0 Clock phase (basic protocol) 1 SPR1 0 SPI master bit rate 0 SPR0 0 " " " "

SPIE

0 = SPI interrupts are disabled 1 = SPI interrupts are enaabled if SPIF and/or MODF is set to one.

SPE

0 = SPI system is turned off. 1 = SPI system is turned on.

MSTR

0 = SPI is configured as a slave. 1 = SPI is configured as a master.

CPOL

0 = Active-high clocks selected, SCK idles low. 1 = Active-low clocks selected, SCK idles high.

CPHA The clock phase bit, in conjunction with the CPOL bit, controls the relationship between the data on the MISO and MOSI pins and the clock produced or received at the SCK pin. CPHA selects one of two fundamntally different clocking protocols to allow the SPI system to comunicate with virtually any synchronous serial peripheral device.

SPR1/SPR0 These two serial peripheral rate bits select one of four bit rates to be used as SCK if the device is a master; they have no effect in slave mode. SPR1 SPR0 Internal Processor Frequency if XTAL Clock divided by is 4.0 MHz 0 0 2 1.0 MHz 0 1 4 500.0 KHz 1 0 16 125.0 KHz 1 1 32 62.5 KHz

From the M68HC05 Applications Guide

Mel.

Thank you Mel,

But 68HC05 and 68705 has different construction, 68705 does not have serial fuctions.

I will expect other thoughts.

This pdf has $0A as misc registers and the bits are described - but they could be different for your micro:-

Geo

Thanks Geo,

The PDF you informed me is maybe the one I was looking for.

Thank You.

micro:-