Yes, they finally got to copy some functions of the AT91 USART ;-)
Yes, but long term it is an advantage to have a consistent family instead of a mix of M3s and M4s. If you go with the early M3s, where is the FPU?
Or implement a spurious interrupt handler in the interrupt controller. The AT91 AIC has been doing this for like 7-8 years..
The Interrupt handler will perform an indirect jump to a vector read from the AIC. If the CPU reads a vector, when no interrupt is present, the SPurious Interrupt Vector is returned instead.
BR Ulf Samuelsson
The problem is that short glitches on the interrupt inputs violate the ARM7 specification. Unless the SoC manufacturer guarantees this workaround works in all cases, I wouldn't recommend it.
On the revision of the ARM7 core I was using, a glitch on the FIQ input would even cause a spurious IRQ when the CPU was already inside another IRQ handler (with IRQs disabled). This would mess up the IRQ LR, even if the spurious interrupt itself was handled correctly. Maybe other revisions react differently.
I believe Atmel's AIC handles this and provides stable IRQ/FIQ signals to the ARM7 core. Any other external interrupt controller should be doing this as well.
The vectored jump through AIC register that Ulf mentioned is really a neat solution overcoming ARM7's limitation.
This is nasty, even if cause/effect is easy to grasp. Back when I was using ARM7 this wasn't even documented. Or I missed it somehow.
Thanks for the interesting tidbit.
I'm not sure what you mean by this. One of the problems that I see with the Kinetis chips is that they are shipping some nominal M4s without the FPU and later ones with the FPU.
Are there any Cortex M3 chips with an FPU?
Mark Borgerson
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