I am attempting to program a 29F010 with a PC parallel port. I am using a CPLD to handle the 16-bit address latching. The CHIP ENABLE is tied to ground and the OUTPUT ENABLE is held high during the program sequence. Once the program sequence is complete, I am attempting to read back the byte that was just programmed. I set the address and bring OUTPUT ENABLE low. However, when I logic probe the OUTPUT ENABLE pin, it never changes to low. I can remove the 29F010 from the circuit and the OUTPUT ENABLE (from the PC) is correct (low). I noticed that the logic probe indicates a brief low pulse on OUTPUT ENABLE as well as a brief high pulse on the CHIP ENABLE (which is tied to ground) when I attempt to bring OUTPUT ENABLE low. This of couse is making it impossible to read the data back. I have been successful in reading the manufacture code and device code so I know something is working correctly. Any ideas why the enable signals are acting this way?
Thanks!!