2-layer board; Layout suggestions

Hi Jay, If there isn't any "real" analog then you don't have much to worry about.

0.1uF or 0.01uF (depending on the speed of the logic family you're using) on each digital IC should do the trick.

That finger approach sounds to me like a way to make the routing work. It isn't the best way to make the circuit quiet.

You're intuition is correct. Is EMI an issue with this product? If it *is* then you should consider doing a 4 layer PCB for that reason alone.

If the layout is sparse enough, this may be just as good as a true 4-layer board. The Vcc doesn't really need its own layer but people rarely make

3-layer boards.

The snake (or "chinese dragon") approach to ground distribution can actually be better than a ground plane for some analog circuits (I'm talking extremely sensitive high gain amplifiers here). The way to make the snake idea work is to remember that *everything* is differrential - each analog stage operates on an input that is *the difference* between two potentials. Understand this and you can route the analog signal ground in your sleep.

But I digress... If there are no gross interfering sources nearby to currupt your digital signals (laser spark gaps? nuclear bombs?) then you will be fine with a bypass at each IC and a Vcc filtered at the regulator. Filling the unused area on one (or both) side with a ground pour wont hurt and will help keep the emissions down.

Bob

I've heard different things about this. One the one hand is the idea that the pcb house would like to save on etchant; on the other hand, I've heard that the pcb house likes to leave as little copper on the board as possible, because the etched copper is recovered from the etch solution and both the copper and the solution can be re-used.

Does anyone know the real story? I suppose it might change over time, depending on the price of copper and the economics of recovering vs. disposing of etchant...

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      Wim Lewis , Seattle, WA, USA. PGP keyID 27F772C1

It makes no difference to the pricing; they don't seem to care one way or the other. *Thin* copper is first etched on a double sided board, then imaged, typically with dry film, and the pattern is then plated up to full thickness, so more copper means less thin etching and more heavy plating (which depletes their anodes).

I like to use copper pour to improve shielding on 2-sided boards. Top for Vdd and bottom for Vss. But first the current flow is taken care of for the power devices, and keepouts put in place to keep the pour from re-routing current through sensitive areas.

Most important is to understand how the currents flow in things like buffers *and* things that go off-board. Reduce loop area, bypass with both electrolytic and ceramic. Watch the Vdd/Vss connections of things like the clock oscillator parts and supply supervisor chips. Avoid having unrelated traces go too near to or under clock oscillator parts and route the common of the load capacitors directly to the Vss pin on the chip (and nowhere else).

Best regards, Spehro Pefhany

--
"it's the network..."                          "The Journey is the reward"
speff@interlog.com             Info for manufacturers: http://www.trexon.com
Embedded software/hardware/analog  Info for designers:  http://www.speff.com

Jay, Get the book, "high speed digital design: the art of black magic" by howard johnson. It is an excelent reference on digital design with some very good information on the physical side of the design (i.e. board layout). While it is a little dated now, it is still an excelent reference. By dated, I mean that he references 1206 and 0805 size chip caps instead of

0603 and smaller and similar things. On the plus side, the inforamtion is right in line with the level of technology that you are referencing.

By the way, has anyone seen Johnson's new book? What is the level of quality, etc.?

Theron Hicks

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> |   ian@redtommo.com       | Windows - just another pane in the
> glass        |
> |   Ian Thompson-Bell
> |                                                 |
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I don't want to appear picky but it seems to me you did not really read my post. There are situations where a 4 layer board is better, and yes four layer prototypes are not that expensive. But as I said, this is a simple low frequency board which the original poster has been asked to layout on two layers, perhaps for cost reasons, he does not say. Gieven these design characteristics a four layer board is not necessary for EMC or any other reason.

Ian

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|   ian@redtommo.com       | Windows - just another pane in the
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|   Ian Thompson-Bell     
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Thank you everyone for your very useful suggestions!

I decided to make bottom layer all GND with spaces for trace, and after I'm done, grow VCC on top to be a big layer.

Yes, I will also watch out for people wanting to clip scopes on the big area on top thinking it's ground...

I had planned on getting the "Black Book of High Speed Design" for awhile, I guess I just got a kick in the butt to do so.

I appreciate information on the EMI related to the finger method, but I'm again, opting to avoid it. It's nice to setup a stable and relatively clean method and work from there rather than use a short-cut simply because the design isn't sensitive.

Thanks again!

-- Jay.