W układzie są AT91..(jw) i pamięć AT24C512. Zapis i odczyt z pamięci działa, ALE.... Podczas testów zrobiłem programik, który zapisuje i od razu odczytuje daną (cztery kolejne bajty) z pamięci (AT24...).
Wysyłając kolejne dane do pamięci:
- zapis danej do TWI_THR i oczekiwanie na sygnał "TWI_SR & TWI_SR_TXRDY" - dana wysłana
- po wysłaniu wszystkich bajtów włączam "TWI_CR = TWI_CR_STOP" i czekam na "TWI_SR & TWI_SR_TXCOMP" - koniec transmisji
- czekam na "TWI_SR & TWI_SR_RXRDY" - dana w TWI_RHR
- po wysłaniu wszystkich bajtów włączam "TWI_CR = TWI_CR_STOP" i czekam na "TWI_SR & TWI_SR_TXCOMP" - koniec transmisji
Problem pojawia się gdy zaraz po zapisie próbuję czytać pamięć. Prgram czeka na "TWI_SR & TWI_SR_RXRDY". Bit ten nie ustawia się. Jeśli pomiędzy zapisem i odczytem dam zwłokę (np. 100msek)czasową, to wszystko chodzi dobrze. Wygląda to tak, jakby pamięć się nie wyrabiała czasowo, albo bit TWI_SR_TXCOMP ustawiał się wcześniej niż faktyczny koniec transmisji. Poradźcie cos koledzy, bo już kur..cy dostaję. Co robię NIE TAK? Zmiana prędkości taktowania TWI nic nie zmienia.
Po zakonczeniu operacji zapisu na I2C kosc pamieci zapisuje odebrane dane, trwa to wlasnie mniej wiecej 3-10ms, zaleznie od pamieci, producenta, itp.
Tu masz cytat z dokumentcaji atmela:
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BYTE WRITE: A write operation requires an 8-bit data word address following the device address word and acknowledgment. Upon receipt of this address, the EEPROM will again respond with a “0” and then clock in the first 8-bit data word. Following receipt of the 8-bit data word, the EEPROM will output a “0” and the addressing device, such as a microcontroller, must terminate the write sequence with a stop condition. At this time the EEPROM enters an internally timed write cycle, tWR, to the nonvolatile memory. All inputs are disabled during this write cycle and the EEPROM will not respond until the write is complete (see Figure 8 on page 10).
PAGE WRITE: The 1K/2K EEPROM is capable of an 8-byte page write, and the 4K, 8K and 16K devices are capable of 16-byte page writes. A page write is initiated the same as a byte write, but the microcontroller does not send a stop condition after the first data word is clocked in. Instead, after the EEPROM acknowledges receipt of the first data word, the microcontroller can transmit up to seven (1K/2K) or fifteen (4K, 8K, 16K) more data words. The EEPROM will respond with a “0” after each data word received. The microcontroller must terminate the page write sequence with a stop condition (see Figure 9 on page 10). The data word address lower three (1K/2K) or four (4K, 8K, 16K) bits are internally incremented following the receipt of each data word. The higher data word address bits are not incremented, retaining the memory page row location. When the word address, internally generated, reaches the page boundary, the following byte is placed at the beginning of the same page. If more than eight (1K/2K) or sixteen (4K,
8K, 16K) data words are transmitted to the EEPROM, the data word address will “roll over” and previous data will be overwritten. ACKNOWLEDGE POLLING: Once the internally timed write cycle has started and the EEPROM inputs are disabled, acknowledge polling can be initiated. This involves sending a start condition followed by the device address word. The read/write bit is representative of the operation desired. Only if the internal write cycle has completed will the EEPROM respond with a “0”, allowing the read or write sequence to continue.
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