VHDL Spørgsmål

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Hej

Jeg sidder og leger lidt med VHDL programmering (for fF8%rste gang). Jeg
er ved at forsF8%ge at lave et LCD interface med VSYNC, HSYNC osv..

Jeg kunne godt tE6%nke mig at vide hvordan jeg kan tildele ben pE5%
FPGA'en til en variabel
f.eks. R0 til R7 nedenfor kunne jeg godt tE6%nke mig tildelt en 8 bit
variabel "RR"

RR 3D% 0xF0;

SE5%ledes at R7 til R4 3D% 1 og R3 til R0 3D% 0

Samtidigt kunne jeg godt tE6%nke mig at lave en stF8%rre variabel kaldet
RGB som indeholder alle tre 8bit variabler sE5%ledes at jeg kan tilgE5% RR
variablen ved at skrive noget ala.

RGB 3D% 0xF00000;

For at fE5% R7 til R4 3D% 1 og R3 til R0 3D% 0 og i dette tilfE6%lde.

Jeg har forsF8%gt at gF8%re ovenstE5%ende nedenfor men det virker
tilsyneladende ikke rigtigt...

Er der nogen der kan sE6%tte mig pE5% rette vej?

entity entityName is port(
-- LCD INTERFACE
R0_105:        out std_logic;
R1_104:        out std_logic;
R2_103:        out std_logic;
R3_102:        out std_logic;
R4_100:        out std_logic;
R5_99:        out std_logic;
R6_97:        out std_logic;
R7_96:        out std_logic;

G0_95:        out std_logic;
G1_94:        out std_logic;
G2_93:        out std_logic;
G3_92:        out std_logic;
G4_89:        out std_logic;
G5_87:        out std_logic;
G6_86:        out std_logic;
G7_84:         out std_logic;

B0_83:         out std_logic;
B1_82:         out std_logic;
B2_81:         out std_logic;
B3_80:         out std_logic;
B4_79:         out std_logic;
B5_78:         out std_logic;
B6_77:         out std_logic;
B7_76:         out std_logic;

PCLK_LCD_57:    out std_logic;
HSYNC_LCD_74:    out std_logic;
VSYNC_LCD_55:    out std_logic;
DEN_LCD_58:    out std_logic;
POL_LCD_59:    in std_logic;
end;

architecture archName of entityName is
begin

type RR is ( R0_105, R1_104, R2_103, R3_102, R4_100, R5_99, R6_97,
R7_96 );
type GG is ( G0_95, G1_94, G2_93, G3_92, G4_89, G5_87, G6_86, G7_84 );
type BB is ( B0_83, B1_82, B2_81, B3_80, B4_79, B5_78, B6_77, B7_76 );
type UV is ( UV7_141, UV6_140, UV5_139, UV4_138, UV3_137, UV2_135,
UV1_134, UV0_132 );
type YY is ( Y7_131, Y6_130, Y5_129, Y4_128, Y3_126, Y2_125, Y1_124,
Y0_123 );

end archName;



Re: VHDL Spørgsmål
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du kan gøre sådan her

signal RR : std_logic_vector(7 downto 0);
 

 
 

-- purpose: saves pins R7 to R0 in variable RR
 

savepins: process (clk, notReset)
 

begin  -- process savepins
 

   if notReset = '0' then  -- asynchronous reset (active low)
 

     RR <= (others => '0');
 

   elsif clk'event and clk = '1' then    -- rising clock edge
 

     RR <= R7 & R6 & R5 & R4 & R3 & R2 & R1 & R0;
 

   end if;
 

end process savepins;


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tror du kan gøre det sådan her

type array2 is array (0 to 2) of std_logic_vector(7 downto 0);
 

signal RGB : array2;
 

 
 

RGB(0) <= R7 & R6 & R5 & R4 & R3 & R2 & R1 & R0;
 

RGB(1) <= R16 & R15 & R14 & R13 & R12 & R11 & R10 & R9;
 

osv

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