FPGA 5V Tolerent

Hej Reppy

Faldt over dette i en 3.3v vs 5v interfacing thread.

Ikke din modstands løsning men ....

Running that 3.3V peripheral at 5V is asking for trouble, especially in the future. It may work, for a while!

Try 74LCX125 - its 5V complient on both input and output side. It can be used going outbound. Use one section for clock and one for MOSI. Connect the enable of each section to ground and you have a non-inverting 5V to 3.3V translator.

MISO side is harder because it wants an open "collector" output that is 5V complient. But, you can use one section 74LCX125 for that also. It has tristate output and each section has its own output enable. Use pullup resistor to +5 (which should already be there). Connect the peripheral's data output to the enable input and, on that same section, connect the normal logic input to ground. You end up with a non-inverting open collector 3.3V to 5V translator! Oh, you may need a

3.3V pullup on the input because the peripheral's output should be open collector.

Andre foreslog disse

74ALVC164245 - 16-bit dual supply translating transceiver (3-State) or 74LVC4245A - Octal dual supply translating transceiver

denne

Your HW guy should be able to show you the data sheets where:

(1) The 3.3V device can generate valid 5V "high" levels. (2) The 3.3V device can tolerate 5V at its input.

If either (1) or (2) are false or unproven, then you do need a level translator. This one

is a clever one which requires only two transistors and 4 resistors. Where the signal is flowing in one direction only, you only need half of the circuit.

dette

You can also use the MAX3377. I use it to interface an MMC (3.3V) to an ATMEGA. It works fine.

dette

Atmel beskriver hvorledes man interfacer deres 3.3v dataflash til en

5v uC.

Måske kan du bruge noget af det

Hørte at Texas giver samples af de der LVC chips

Hilsen Carsten /Cfo

sikker på der ikke står, noget ala' Vio +0.5V ?

Når input spændingen kommer ~0.5V over io spændingen begynder ESD dioderne at lede, så spændingen kommer ikke højere, men der er grænser for hvor meget strøm de kan klare derfor de 10mA

Du skal ha' en serie modstand der begrænser input strømmen ved den højest input spænding du har tænkt dig at sende ind i en input, med mindre den spænding er mindre en Vio+0.5

dvs. Ved 5V* : 5V-3.3 = 1.7V, 1.7V / 10mA = 170 Ohm

Men det hjælper kun på tilfældet hvor FPGA'en kun er input, hvis det skal snakke med 5V logic skal du sikre dig at mininum output fra FPGA er nok. Med rigtige TTL burde det ikke være et problem

De sidder der sikkert også fordi de hjælper på reflektioner

-Lasse