Unfamiliar FET and capicitor schematic symbols

Do you have a question? Post it now! No Registration Necessary

Translate This Thread From English to

Threaded View
In the simplified schematic for the Analog Devices AD825 there are two symb
ols I haven't seen before. One of them is an FET symbol and the other is a  
capacitor. These can be seen in Figure 32 on page 10 of the AD825 datasheet
. The POS and NEG inputs each go the gate of FETs with this symbol. The cap
acitor symbol is labeled Cf and are connected to VOUT. Not sure if whay I'm
 looking at for Cf is unique symbol or it just indicates a layout feature.

Thanks in advance.

Re: Unfamiliar FET and capicitor schematic symbols
On 01/10/2017 11:05 AM, snipped-for-privacy@gmail.com wrote:
Quoted text here. Click to load it

The circle on the FET inputs means that they're PFETs.  (It's like the
circle on an inverter output--they pull high when the gate goes low.)

I've never seen the capacitor symbol, but on a SWAG it looks like
they're showing which end of the cap is the top metal layer.  Rolled
film and oil+paper caps have markings for which lead is the outside
foil.  (This makes a big difference in their vulnerability to capacitive
pickup.)

Cheers

Phil Hobbs

--  
Dr Philip C D Hobbs
Principal Consultant
We've slightly trimmed the long signature. Click to see the full one.
Re: Unfamiliar FET and capicitor schematic symbols
On Tue, 10 Jan 2017 11:27:59 -0500, Phil Hobbs

Quoted text here. Click to load it

It's the TUB connection... the TUB is the isolating
region/diffusion/implant that the capacitor is built into.

It is likely a junction capacitance, but could be metal-over-Silicon
(MOS).

Metal-over-metal (MOM) caps typically/simply include a label, "TOP" or
"BOT"
        
                                        ...Jim Thompson
--  
| James E.Thompson                                 |    mens     |
| Analog Innovations                               |     et      |
We've slightly trimmed the long signature. Click to see the full one.
Re: Unfamiliar FET and capicitor schematic symbols
On 01/10/2017 11:40 AM, Jim Thompson wrote:
Quoted text here. Click to load it

Interesting, thanks.

Cheers

Phil Hobbs

--  
Dr Philip C D Hobbs
Principal Consultant
We've slightly trimmed the long signature. Click to see the full one.
Re: Unfamiliar FET and capicitor schematic symbols
On Tue, 10 Jan 2017 14:17:01 -0500, Phil Hobbs

Quoted text here. Click to load it

Mostly I roll my own symbols in such a way that I can be sure to get
those tub biases correct in the schematic, such that they netlist
correctly, critical to getting the Silicon layout correct, and getting
proper first-pass chip performance ;-)
        
                                        ...Jim Thompson
--  
| James E.Thompson                                 |    mens     |
| Analog Innovations                               |     et      |
We've slightly trimmed the long signature. Click to see the full one.
Re: Unfamiliar FET and capicitor schematic symbols
On Tue, 10 Jan 2017 12:25:13 -0700, Jim Thompson

Quoted text here. Click to load it

I should have added that _symbols_ are simply visual aids for the
human examiner... what matters is not directly visible on the
schematic, the underlying _template_ which defines how the symbol
netlists.
        
                                        ...Jim Thompson
--  
| James E.Thompson                                 |    mens     |
| Analog Innovations                               |     et      |
We've slightly trimmed the long signature. Click to see the full one.
Re: Unfamiliar FET and capicitor schematic symbols
On Tue, 10 Jan 2017 12:28:30 -0700, Jim Thompson wrote:

Quoted text here. Click to load it

In the case of that schematic there's a good chance that it was done by  
some drawing program, by whatever person was tasked with making the data  
sheet pretty.

--  

Tim Wescott
Wescott Design Services
We've slightly trimmed the long signature. Click to see the full one.
Re: Unfamiliar FET and capicitor schematic symbols
On Tue, 10 Jan 2017 18:03:27 -0600, Tim Wescott

Quoted text here. Click to load it

PSpice Schematics DO netlist properly.
        
                                        ...Jim Thompson
--  
| James E.Thompson                                 |    mens     |
| Analog Innovations                               |     et      |
We've slightly trimmed the long signature. Click to see the full one.
Re: Unfamiliar FET and capicitor schematic symbols
On Tue, 10 Jan 2017 17:16:04 -0700, Jim Thompson wrote:

Quoted text here. Click to load it

But did that schematic come out of PSpice?


--  

Tim Wescott
Wescott Design Services
We've slightly trimmed the long signature. Click to see the full one.
Re: Unfamiliar FET and capicitor schematic symbols
On Wed, 11 Jan 2017 22:05:06 -0600, Tim Wescott

Quoted text here. Click to load it

I'm still running original-crispy-flavor PSpice Schematics before the
OrCAD abortion and the Cadence take-over.  Fabulous tool-set!
        
                                        ...Jim Thompson
--  
| James E.Thompson                                 |    mens     |
| Analog Innovations                               |     et      |
We've slightly trimmed the long signature. Click to see the full one.
Re: Unfamiliar FET and capicitor schematic symbols
:
Quoted text here. Click to load it
mbols I haven't seen before. One of them is an FET symbol and the other is  
a capacitor. These can be seen in Figure 32 on page 10 of the AD825 datashe
et. The POS and NEG inputs each go the gate of FETs with this symbol. The c
apacitor symbol is labeled Cf and are connected to VOUT. Not sure if whay I
'm looking at for Cf is unique symbol or it just indicates a layout feature
.
Quoted text here. Click to load it

Thanks very much for all the replies.

Re: Unfamiliar FET and capicitor schematic symbols
snipped-for-privacy@gmail.com wrote...
Quoted text here. Click to load it

 Datasheet says, "With its unique input stage design..."
 and the draftsman is making sure we get the point.  :-)


--  
 Thanks,
    - Win

Re: Unfamiliar FET and capicitor schematic symbols
On Tue, 10 Jan 2017 08:05:39 -0800 (PST), snipped-for-privacy@gmail.com wrote:

Quoted text here. Click to load it

On the FET, + symbol just indicates back gate (tub) is tied to VPOS.

Likewise, on the capacitors, extra plate is the tub that the capacitor
sits in... for your purposes, the stray capacitance.
        
                                        ...Jim Thompson
--  
| James E.Thompson                                 |    mens     |
| Analog Innovations                               |     et      |
We've slightly trimmed the long signature. Click to see the full one.

Site Timeline