Unexpected PIC32 behavior

Does the chip get hot when SS is at 1.2V?

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs 
Principal Consultant 
ElectroOptical Innovations LLC 
Optics, Electro-optics, Photonics, Analog Electronics 

160 North State Road #203 
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Check your CONFIG bits, that is usually where most problems arise with the shared I/O pins.

Cheers

Warm. I just found out if I comment out the SPI init code, the circuit current drops by 60ma! Here I thought my display was pulling all that current...

I put a pullup resistor on the (now input) pin, and it reads near vdd, like it should.

I can declare it an output, and get proper vss/vdd by setting it hi/lo, so it's not a short on the pin.

Now I'm suspicious of the Slave Select pin remapping - and not at all sure what to change.

You may not want to hear this, but don't always assume YOU'VE done something wrong. Years ago, I once had my software department spend six weeks out of a tight schedule to chase down a weird effect only to find that the manufacturer's [remain nameless, since they've cleaned up their act] FPGA's moftware did NOT do what it said it did. In other words, the simulations were NOT converted properly into programming the hardware!! Needless to say, at the time we went with a different manufacturer, problem solved.

[snip]

That's certainly a possibility. I may have to check out Microchip's errata on the '150 to see if there's a known issue.

Ain't learning curves fun?

Have you verified that you don't have a short to another pin? Getting

1.2V on a wire when the logic is powered by 3.3V sounds a lot like two output pins having an argument about whether that wire should be a 1 or a

1.2V isn't exactly 3.3V/2, but pull-downs tend to be stronger than pull- ups, and the two pins may not be on the same chip anyway.

--

Tim Wescott 
Wescott Design Services 
http://www.wescottdesign.com

You have not given the whole part number, and I'm not going to plod through more than one errata, but this might be relevant:-

Voh of 1V sure sounds like some kind of internal contention.

--sp

That was the norm about 15 years ago. I had the boss buy a Synplicity-Pro seat to get even simple designs to synthesize into something that worked. At the time, Synplicity-Pro was something like $25K for the license, plus $5K per year. The good part was that it made the justification for the $4K laptop easier. Of course, I had to buy two so I always had a backup, which I let the boss use. ;-)

[snip]

I've checked continuity between adjacent pins and traces - nada.

I disabled the spi, and made it a gpio. set high=3.3v, low=0v. The spi pins are currently not connected; they go to to an off-board connector.

[snip]

PIC3mx150f128b.

Interesting. I am trying to make RA0 my ss pin. I'll have to check out various settings when I've recovered from the soccer team's year-end windup! ;)

Thanks!

Errata here:

Module: I/O Ports Output High Voltage (VOH) on the RA0 and RA1 pins is not within the published data sheet specification if the I2C1 module is enabled. In addition, internal capacitance on these pins is one and one-half (1.5) and two times higher, respectively, than other I/O ports. Work around Disable slew rate control of the I2C1 module by setting the DISSLW bit (I2C1CON). There is no workaround for higher capacitance

Best regards, Spehro Pefhany

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speff@interlog.com             Info for manufacturers: http://www.trexon.com 
Embedded software/hardware/analog  Info for designers:  http://www.speff.com

[snip]

Downloaded, thanks. No mention of excess current draw when SPI ports are enabled; RA1 is not affected. AFAICT, just RA0.

Time for some bit-twiddling...