Could some electronics guru please help ? Is there any commonly available reference design for an ultra low frequency voltage controlled oscillator ? I developed a 60 Hz center frequency SPICE model using common op-amps. I was wondering if there are any reference designs out there. Any feedback would be very useful. Thanks in advance for your help.
There's one on the LM324 datasheet that will be happy enough at 60Hz, plus it only uses 10-15 cents worth of parts.
Best regards, Spehro Pefhany
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Unsophisticated and fixed one could use three components? From a DC (or rectified AC) source of more tha 100 volts. A resistor, a neon and a capacitor. Size of capacitor determines rate. I think it used to be called a 'Relaxation oscillator'?
I'd hardly call 60Hz "ultra low frequency". But it is pretty darned low.
All the suggestions you've gotten so far are good as far as they go and may well be perfect -- but what are you trying to do? Do you need sine wave out or square? If sine wave, how pure? Do you have any specifications on jitter, phase noise, or frequency accuracy?
You could digitally synthesize a 60Hz sine wave with a smallish processor -- I believe there are some TMS430 parts that could do it all in one package with a PWM output to be filtered by a simple RC.
But "best" depends heavily on what you want.
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Tim Wescott
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Do you need to implement control loops in software?
"Applied Control Theory for Embedded Systems" was written for you.
See details at http://www.wescottdesign.com/actfes/actfes.html
Buy a sine/cosine potentiometer, and put a motordrive on it with a reduction gear . Motor speed and gear will determine frequency, and supply voltage to the pot. will control amplitude.
Or use a computerchip with ad channel to produce any signal you want. With a 16-24 bit audio ad chip it should work very well.
In different contexts ultra low frequency might refer to something with one cycle every second, hour or even weeks.
While very low frequencies could in principle be generated with traditional RLC components, the physical dimensions would become huge and in practice capacitor leakage resistance and coil series resistance would finally limit how low you could go.
However, a digital circuit followed by a DAC could go as low as you want, however common audio DAC frequency response drops at about 3 Hz, limiting how low you can go with such components.
From a "needs huge analog components to work" it's not ultra low to me
-- but yes, from an RF standpoint it's below Ultra Low.
I'd just use a general-purpose DAC for this, if I didn't PWM-and-filter.
But, how far this needs to go depends on what the OP really needs, and he hasn't weighed in yet.
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Tim Wescott
Wescott Design Services
http://www.wescottdesign.com
Do you need to implement control loops in software?
"Applied Control Theory for Embedded Systems" was written for you.
See details at http://www.wescottdesign.com/actfes/actfes.html
I am trying to design a PLL for very low frequencies, e.g., power line grid. I am concerned with the VCO as it is a crucial sub-circuit. I am aiming for a phase noise of approximately -100 dBc/Hz but not very sure of the offset frequency. Ideally, I would like to have frequency accuracy of 1 - 5% at most. Also, I am aware that S-parameter methods are not appropriate at these low frequencies.
I think that those specs would be difficult to achieve with an all-analog oscillator running at 60Hz. Not impossible -- I could do it, and Joerg could do it in a fraction of the time I'd take. Using some sort of direct digital synthesis -- even if it's just a microprocessor
-- running off of a crystal reference would be almost trivial in comparison and would probably take less board space and would be far more repeatable in manufacturing.
If you just had to do this purely in the analog domain your best bet might be a pair of crystal oscillators, frequency steered with varactors, carefully built, and with their outputs mixed down to 60Hz. But that's a solution I would expect to see in a bit of kit from the
50's through the 80's -- anything later and I'd expect to see a DDS.
I think in another response I mentioned a TMS430 -- use one of those (or a PIC on an AVR or a Stellaris, etc.) with the right ADC, and you can build the whole PLL application into the software, and probably whatever measuring you're planning on doing as well.
--
Tim Wescott
Wescott Design Services
http://www.wescottdesign.com
Do you need to implement control loops in software?
"Applied Control Theory for Embedded Systems" was written for you.
See details at http://www.wescottdesign.com/actfes/actfes.html
call 60Hz "ultra low frequency". =A0But it is pretty darned low.
ne
Have you thought about a current charging and discharging a cap? This gives a nice triangle wave with the frequency proportional to the current. Just make sure the voltage that defines the 'trip' points is clean. (A mistake I made.) Or do you need a sine wave?
It's not so much that S-parameter methods won't work, though (they will, just fine). It's just that S-parameter methods are designed to really be useful where lumped-circuit approximations don't hold. At 1GHz, that happens if the circuit spans a good portion of your hand -- but at 60Hz, that doesn't happen until the circuit spans a good portion of the continent.
Unless you've totally forgotten how, use lumped-circuit analysis and it'll work just fine.
--
Tim Wescott
Wescott Design Services
http://www.wescottdesign.com
Do you need to implement control loops in software?
"Applied Control Theory for Embedded Systems" was written for you.
See details at http://www.wescottdesign.com/actfes/actfes.html
If you want to track the _actual_ mains frequency, just use a mains driven synchronous motor. To get the noise sidebands down, use some flywheels :-).
Just a few minutes ago, the Nordel AC network (Danish isles, Finland, Norway, Sweden) was running at 50.11 Hz or +2200 ppm above nominal in order to allow the mains synchronized clocks to catch up.
A simple fundamental frequency VXCO can be pulled about +/-100 ppm with the load capacitance. About 1000 ppm is the maximum with adjustable serial inductance and adjustable parallel load capacitance at the crystal.
At 50/60 Hz, even a trivial processor can generate a variable frequency sine wave using the NCO (Numerically Controlled Oscillator) principle to generate a sine wave, which can be locked to the incoming signal in some loop configuration.
Even a trivial processor might be able to generate both sine and cosine waveforms for 49.98, 50.00. 50.92 Hz etc. in parallel and performing a phase comparison between all these in parallel to determine the best match.
Way noisy. You may as well use a Wien bridge oscillator.
Basically the phase noise of an LC oscillator is closely related to the noise of the amplifier divided by the loaded Q of the tank circuit. In the case of an RC oscillator (i.e. anything that doesn't use a real resonant component) the 'loaded Q' is less than unity, which makes achieving that -100dBc phase noise spec difficult.
(Why so low, by the way?).
--
Tim Wescott
Wescott Design Services
http://www.wescottdesign.com
Do you need to implement control loops in software?
"Applied Control Theory for Embedded Systems" was written for you.
See details at http://www.wescottdesign.com/actfes/actfes.html
An LC type oscillator is good for phase stability (multivibrator types are less good), but C values of voltage-variable capacitors are inconvenient for this range. So, you're stuck with an increductor. This is an inductor with a semi-saturating core, using a high impedance winding with DC current in it to move the inductance.
It's an old technique (usually nowadays this kind of thing is only used for flux-gate magnetometers) but a goodie.
Switched-capacitor filters with a 100x clock are another approach. I think the MF10 app note has an example (figure 7).
The fast clock can be a relatively unstable CD4046 type of VCO, it'll all average out. Hopefully.
Yikes, it would take years (decades) to measure that. Your reference standard to measure against would be problematic as well. One cycle (about 16.667 ms) * 10^10 is over 46,000 hours, 275 weeks, 5.2 years.=20
How about reframing it as a jitter and wander specification?
You would blow the phase noise spec by being off by fractional millihertz.
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