TRIAC gate control problem

My first thought is that you have a mains signal to the processor which is being clamped to 0-5V by the input protection diodes of the processor. On some ICs this causes a signal on other pins.

I always clamp signals that could exceed exceed either supply with a BAT54S dual shottky diode. This prevents a signal forward biasing input protection diodes.

You can easily check for this with a scope. Make sure no pin goes outside the supply by more than about 0.3V.

roduct.do?id=3D2N6073A

Why don't you buffer the processor output with a device that has got a decent pull-down capacity? An NPN transistor or a logic level MOSFET would be the traditional choices; you will have to add a pull-up resistor from collector/drain to +5V to turn the triac on when the buffer devies isn't pulling down, and you'd need a second resistor between the base of the bjt and and the processor output to define the base current.

This kind of simple buffer does invert the signal, so you'd want to modify the processor software accordingly, but that should be trivial.

-- Bill Sloman, Nijmegen

"dgleeson422111"

** That is a very sensitive gate triac with a low commutating dv/dt - ie 5V/uS.

** There is no such animal.

** You are chasing a ghost as that 0.2 volts is simply not the problem, there is no need to pull the gate low.

Normally any un-triggered triac will self commutate "off" as soon as the MT1 to MT2 current falls below the holding current level - ie about 5-10 mA for the device in question.

It can however immediately re-trigger to the "on" state if there is even the briefest a voltage spike applied across the same load carrying terminals as a result of that self commutation. Inductive loads will generate just such voltage spikes.

For this reason, it is standard practice to add a "snubber " network across MT1 and MT2 to damp any such spike voltage - usually consisting of a 47-

100nF cap ( mains rated of course ) with a 50 - 100 ohm resistor in series.

Give it a go.

..... Phil

Is the ATtiny really guaranteed to supply enough current to reliably trigger that triac in both of the quadrants you are using, and over temperature and unit-to-unit variations?

I suggest swapping the triac for a Teccor alternistor or other "snubberless" triac and adding a buffer (Triacs work better with negative gate drive, BTW, so quadrants II and II. They are most insensitive in QIV (positive gate, negative MT2)-- some are not even specified.

Sensitive-gate triacs tend to be more susceptible to lack of commutation from dv/dt.

A triac gate can act as a low impedance low voltage source when it is on, which could cause your processor to malfunction if connecte directly. (It can also act as a low impedance *high* voltage source if the triac or a connection fails).

Best regards, Spehro Pefhany

--
"it\'s the network..."                          "The Journey is the reward"
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roduct.do?id=3D2N6073A

I'd use an opto-coupler with it. The opto-coupler will have a spec for the led current, just use the right resistor in series with it for you 5v. Also prevents you from having your logic side physically connected to the mains. Safety issue in case of component failure.

You don't say much about the load. As someone already points out a inductive reactive load can easily cause the Triac to stay on.

I had a similar problem. Heater controller was working OK but the triac seemed to be firing for random lengths of time - not with the on/off PWM proportional control it was designed for.

The heater was a long length of nichrome wire coiled into a large quartz tube that worked as an immersion heater down in a laboratory media reservoir. I calculated the inductance based on a single layer solenoid wound coil, using a formula from the Amateur's Radio Handbook. Then calculated the capacitive reactance needed to cancel the inductive reactance, and put it across the heater with a low value series resistor to lower the Q, and the thing behaved perfectly.

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Dang Phil, I have no idea if your right! But it's certainly what I'd try first!

I must admit I love your posts,

George Herold

Yup, and make the resistance in the capacitance branch equal to the resistance in the inductive branch. C =3D L/R^2. OK it's a bit late (a few too many beers) and I'm guessing I got that equation wrong. But it's something like that. This is my favorite trick for driving inductive loads. Make the load look purly resistive to the amp driving it.

George Herold

[Snipped]

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There are several other similar devices available at digikey. These are of course opto-isolated Triacs - not "isolated gate" Triacs. Regards Anton Erasmus

ISTR reading in an application note that triacs work better with negative gate voltage, making Vcc the ground reference would turn your pull-up into pull-down.

An alternative would be to drive a triac O/P opto-isolator with your micro and using that to control the main triac gate - this would give your micro excellent protection as well.

Others have mentioned snubbers - you do have one don't you? (or use snubberless triacs).

Semi

Optical isolation is an excellent way, but.... On one side there is AC withits neutral (ground), and the other side is the MPU, its isolated supply, inputs and drivers. My question is what should be used to tie these grounds together to prevent ESD (and other damaging voltages)?

On a three wire system, you'd use chassis ground for EMI ESD protection. AC neutral is only tied to ground at the service entrance where there is (should be) a wire to a stake into the earth. The neutral and ground, for distribution, come together at the circuit breaker panel.

There is (should be) a ground at the step down distribution transformer too. That one can go missing if its a pole transformer, since copper prices are up.

Our thieves are stupider - they keep digging up fibre-optic cable!

neutral is *not* ground.

The OP may have cost constraints that prevent an isolated supply for the MPU.

floating an isolated MPU w/ I/O might be fine. Tying the MPU to the line can also work. Or, you can use the 3rd wire (earth ground, not neutral) if you have it - you might not have it. A lot depends on the I/O, which hasn't been described.

I wonder if the OP has the knowledge to make a safe and reliable design. From the description of the problem, I'm doubtful.

Bob

Say the MPU inputs are switches that go from MPU gtound to MPU supply and outputs drive optically isolated triacs. Those triacs switch solenoids that are tied to 480/240/120VAC inputs and their return (relative ground so to speak) is neutral. What is the standard / safety scheme that is used to tie the MPU ground to that neutral? A resistor between 10K and 1meg? A capacitor? What?

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Depends on locale. Locale defines the electric distribution properties. These then drive what is good safety in equipment design.

If the processor pin pull-down capability is low, the gate is practically floating and hence sensitive to any leakage through the triac or capacitively coupled inside the triac or in the circuitry.

Using a buffer stage between the processor and the gate that actively pulls up/down, creating a low impedance path for the gate leakage.

How is the circuitry connected ?

I assume that the load is from Live to MT2 and MT1 is connected to Neutral. How are the MPU Vcc and Gnd terminals connected ? Do you have MPU Gnd connected to Neutral, i.e. Vcc is +5 V relative to Neutral or did you connect MPU Vcc to Neutral and MPU Gnd is at -5 V relative to neutral ?

Look carefully at the diagram in the triac data sheet, there is a 7400 gate driving the gate through a resistor, the power supply pin 14 (Vcc) is connected to MT1 and hence Neutral and pin 7 (Gnd) is connected to -5 V. This would also explain why other say that this triac works better with a negative supply.

So you really would have to generate a -5 V (relative to neutral) power supply for the MPU Gnd and you could get away even with the buffer.

Paul

I my case, there is no connection between the MPU and AC Neutral (yet). So, it seems you advocate a direct connectionfrom MPU ground to AC Neutral.

"Paul Keinanen"

** The " gate " terminal of a triac is nothing like the gate terminal of a mosfet or IGBT.

It does not need to be "pulled low" as it has an inherently low self impedance in both polarities - normally there is an internal resistor connected from gate to cathode of between 50 and a few hundred ohms.

Combine this fact with gate threshold voltages of 1.5 volts in both polarities and trigger currents of around 5 to 50 mA and you see the devices are not gate sensitive at all.

..... Phil