Thermometer Code Chip

Pretty much everything 10(+) bit-ish and high-speed from Analog devices,

like the AD9257 or whatever else that starts with AD92... or AD96...

Dimitrij

Reply to
Dimitrij Klingbeil
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The LTC2242 family goes from 125 MHz/10 bits up to the one we use,

250/12. Pipeline delay is 5 clocks.

Here's one on a board, 12 bits of LVDS into an Altera FPGA, at 250 MHz.

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We are seeing less than 1 LSB of RMS noise. That was shocking, especially considering all the switching supplies an inch or so away.

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John Larkin         Highland Technology, Inc 
picosecond timing   laser drivers and controllers 
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Reply to
John Larkin

Six of one, a half-dozen of the other... :)

The LT part John mentioned must be such a mixture, with a pipeline delay less than NOB. Of course, it could always be 100% flash with serdes pipelines, but... why?

Subranging, yes, that's a good word for it.

Tim

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Seven Transistor Labs 
Electrical Engineering Consultation 
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Reply to
Tim Williams

This is not a pipelined SAR converter. From page 18 of the data sheet...

"Each stage of the pipeline, excluding the last, consists of a low resolution flash ADC connected to a switched-capacitor DAC and an interstage residue amplifier"

Pipelined - yes. SAR - no. This is just an extension of the subranging flash converter I was talking about.

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Rick
Reply to
rickman

I'm not sure what you are saying. They are clearly pipelined, but flash and not SAR.

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Rick
Reply to
rickman

Yeah, that's what I mean.

At a glance, here's an example like I was thinking of earlier (and as Dimitrij mentioned):

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12 bits, propagation delay 16 cycles.

Tim

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Seven Transistor Labs 
Electrical Engineering Consultation 
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Reply to
Tim Williams

I'm not following what you are saying. This is another pipelined flash part, not SAR. It has the exact same text on page 25 saying each pipeline stage has a low resolution flash converter. Maybe they are not describing it well and these are SAR converters. I don't know why it would take 16 clocks for a subranging converter. But I do know they need to do corrections so that may take some of the extra clock cycles.

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Rick
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rickman

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