phase lock loop (PLL) HELP

You'll have to be a bit more specific than that. How far have you got? What don't you understand?

Hi, Biras. You're not the only one who "feels trouble" in loop filter design. ;-)

you say you've got a 40-70 Hz input signal and a 4046. You'd like to use the 4046 PLL to generate and lock a 256KHz to 448KHz signal. You've got a 5VDC power supply. You're stuck on the loop filter, and this apparently isn't a homework problem.

If you're looking for a "cookbook" answer, you should look at the end of Chapter 7 of Don Lancaster's CMOS Cookbook, available from many libraries as well as from amazon.com or through Mr. Lancaster's website:

He discusses the 4046 in enough depth to allow you to get a good start, and hack a loop filter together that's good enough. Assuming you have a clean digital CMOS-level input signal (needn't be 50% duty cycle), Mr. Lancaster might have you start out with the wideband phase detector (wider range, more stable, no requirement for 50% duty cycle on either input) and something like this (view in fixed font or M$ Notepad):

` 470pF ` ___ || ___ ` .--|___|-. .--||--. .-|___|-. ` | 10K | | || | | 15K | .---------. ` | | | | | | | | ` === 11| |6 7| |12 === | +12V | ` GND .-----o--o------o--o-----.GND | |\\| | ` | | '---|-\\ | V(t) ` 5| 200KHz-500KHz |9 | >--o---o ` .-----o VCO o-------o----|+/ ` | | (1/2 CD4046) | | |/| ` | | | | -12V ` === '-----------o------------' | ` GND 4| | ` o--------------------(-------o ` | | f(out) ` .-----------o------------. | 256-448KHz ` | | | ` | Divide-by-6400 | | ` | Counter | | ` | (U-Do-It) | | ` | | | ` '-----------o------------' | ` | | ` 3| | ` .-----------o------------. | ` | | | ` 14| Wideband Phase | ___ | ___ ` o----------o Detector 13 o-|___|-o-|___|--. ` f(in) | (1/2 CD4046) | 1M 100K |+ ` 40-70Hz | | --- ` '------------------------' 1uF --- ` Tantalum| ` === ` GND (created by AACircuit v1.28.5 beta 02/06/05

The values for the two resistors and the cap for the VCO come from the equations in the datasheet (but please check for yourself -- no guarantees on the maths at these prices). The design of the loop filter at the output of the wideband phase discriminator is of course the most important part of the circuit. Mr. Lancaster suggests the "fire, ready, aim" method here. By his cookbook method, you would apply a step change to the input signal frequency, then observe the effect on the loop filter output/VCO input node (pin 9), and change the filter components iteratively to get the response you need. You would use a high input impedance, fairly fast op amp to monitor the voltage V(t) without bogging down the loop filter cap with the input impedance of your meter. You should also monitor the output on pin 1 to see if a good lock is occurring.

It wouldn't be fair to Mr. Lancaster to go through the whole technique here -- and I believe this is the best part of the book. Not cricket to give it away and all. I highly recommend you buy, beg or borrow his CMOS Cookbook, and look at his treatment of the 4046. Using it with an oscilloscope, a newbie or digital guy can actually make a lower frequency PLL work pretty well (which is good enough, most of the time) without the maths. But I can almost guarantee it won't be good enough unless you go through the technique to trade off between loop settling time and damping for your application. If you've got a high impedance input fast op amp (like the LF411) to buffer pin 9, all you need is the scope. I can guarantee that, with the book in one hand and scope probe in the other, you should get a satisfactory answer to your puzzle (at least as long as you're not asking for anything unreasonable from the loop filter).

Not only that, but after all, the loop filter is supposed to be tailored to your needs. You neglected to mention any of your loop filter requirements. The above circuit is likely too slow for what you need.

You don't need the op amp in your final circuit, of course.

If you are interested in the maths, look at "Phaselock Techniques" by Floyd Gardner.

Good luck Chris