According to Dr. Howard Johnson's book, which describes it more susinctly than I could, there are three "rules" of what a power supply system must accomplish in digital logic for proper operation.
Rule 1: You must have a low impedance ground connection between the gates in order to prevent common path noise due to the return currents
Rule 2: The impedance between the power pins on any two gates should be just as low as the impedance of the ground pins to provide a stable voltage to the devices.
Rule 3: There must be a low impedance path between the power and ground.
Basically in order for the logic devices switch, from high - low or low
- high, electrical charge must be moved, ie current must flow. The current that flows can have a significant magnitude and a fairly high frequency content. In order to prevent these switch currents from disturbing the rest of the system, bypass capacitors are used to source the necessary current.
Here is a link to the Howard Johnson's website that discusses bypass capacitors.
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I too had never heard of them or even really considered their use until I started to get bit by noise issues in a field released product line. The capacitors should also be of a material that has a low ESR, or equivalent series resistance which is basically a parasitic resistance that can be modeled as being in series with the capacitor, limiting its effectiveness. Typical values for bypass capacitors are about .1uF, though use of .01uF and 1uF are both common depending on the speed of the device. Note that speed is relative to the signal rise and fall time, not the clock speed.
In addition to the bypass capacitors, a ground plane is one of the few structures that will provide a low impedance path for the return currents. WIth a proper ground plane and use of bypass capacitors, the power routing can be pretty much arbitrary.
If a proper ground / power system is not implemented, the power system will bounce as devices switch. The devices, which internally can be viewed as a comparitor can't tell the difference between this power bounce and a desired signal and will react if the bounce is serious enough.
Another arguement you may encounter is people saying that I am only using simple logic gates, or older stuff, etc, nothing new and high speed. Again, the important (but difficult point to grasp) is that the speed is not related to the operational or clock speed. It is a function of the IC design. Even 74ls devices, manufacturerd on more modern equipment can exihibit rise and fall times much faster than in years past.