One-shot triggered rising and falling?

Hi all,

I'm sure someone has an quick answer for this. I'd like a simple circuit or a part that produces a pulse -- basically a one-shot -- with both a rising edge and falling edge input signal. All the multivibrator ICs I have seen will trigger on rising OR falling, but not on both. How can I get a trigger on both?

Thank you!

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Douglas Beeson
Reply to
Douglas Beeson
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I would use a quad XOR to build an edge detector: wire three of the XORs as non-inverting buffers and put them in series, connect the output of this s eries string to one of the inputs of the fourth XOR, and wire the other inp ut of the fourth XOR to the input of the first of the three series XORs. T his will produce a narrow pulse on both polarity edges of the input. The w idth of the pulse will be the propagation delay in the series string (when I did it a long time ago with standard TTL, the spec sheet gave the delay a s 10ns/gate, but when I measured it, it was closer to 3-4 ns). If these pu lses are too narrow, you and increase the propagation delay by putting some small capacitors to ground at the interior nodes of the series string.

Reply to
jfeng

If you take advantage of progation time with inverters you can create a inverted pulse of the original but with a enough gap between, to possibly retrigger the one shot circuit on the down side.

you combine two open collector type inverter outputs, one of them being past down lets say 3 inverters and the original using only one inverter.

As long as the one shot responds to that you're all set.

Jamie

Reply to
M Philbrook

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You could use either a 74HC123 or a CD4538. 

Make one of the one-shots in the package negative triggered, one 
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Reply to
John Fields

jfeng has suggested feeding the two inputs of an XOR (such as CD4070) with the direct signal on one, and a delayed signal on the other. You can get that delay from propagation delay of multiple gates, as he suggests.

An alternative (which I first saw in the "CMOS Cookbook" by Don Lancaster) is to use a simple RC delay and a single XOR gate. You connect the signal directly to one gate input, and through an R to the other (with the C going to ground).

This gives you some adjustment flexibility for noise rejection, etc, if you don't mind adding the discrete RC parts. You also may find other uses for the remaining 3 XORs in your CD4070 (or whatever).

Best regards,

Bob Masta DAQARTA v8.00 Data AcQuisition And Real-Time Analysis

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Reply to
Bob Masta

From ~1980....

May need some adaptation to fit your needs. ...Jim Thompson

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| James E.Thompson                                 |    mens     | 
| Analog Innovations                               |     et      | 
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Reply to
Jim Thompson

You can do the XOR trick that others have suggested, but you could also use a dual one-shot.

This is a tach circuit that uses both edges.

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John Larkin         Highland Technology, Inc 
picosecond timing   laser drivers and controllers 
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Reply to
John Larkin

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1. What output pulse width would you like? 

2. Do you want the same output width for both high and low going 
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Reply to
John Fields

Reply to
John Fields

I think the request was for a simple circuit.

No kidding!

Reply to
jfeng

I suppose there are a lot of Beesons, but do you know of a physics professor at LSUNO, ca 1965?

Reply to
John Larkin

No, not in my close family line. Legend has it there were "northern Beesons" who went to Ohio after the Revolutionary War and "southern Beesons" who went to Alabama and elsewhere. All the well-known Beesons (except for Chalkley Beeson, my great-great uncle - Google him) came from the southern line.

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Douglas Beeson
Reply to
Douglas Beeson

Hi John,

Sorry about the long delay answering. Went to Europe for two weeks with practically no access to internet.

No narrower than about 6 ns. I am using it to clock a SN74LVC1G175 flip-flop (your idea, actually, some time ago..). 20-100 ns would be ideal.

Yes.

No, it should be non-retriggerable.

I have seen the suggestion for an XOR with an RC delay circuit. I think that might work just fine here. Thoughts?

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Douglas Beeson
Reply to
Douglas Beeson

Thank you all for your suggestions. I like the XOR approach, especially the single gate with an RC delay. My timing requirements are not super tight. The output needs to clock a flip-flop that can handle up to 175 MHz - so around 6 ns pulse width minimum. My application will work just fine with 100 ns -- or even wider -- pulse widths, so I am thinking a 1k resistor and a 1 nF cap as RC.

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Douglas Beeson
Reply to
Douglas Beeson

Thanks for this idea. I have been away from the bench for a while but have tried it out on Spice and a 1k resistor and 1nF cap seems to work just great for me.

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Douglas Beeson
Reply to
Douglas Beeson

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