Counter ICs

Examine this java-coded display of one:

It's a 5-bit ring, but the output of the last bit is inverted and fed back so it takes two loops through to repeat itself completely.

Jon

Hi, you've found a data-sheet that's a really good start.

actually it's a 5 bit shift register fed back it's inverted output then run through a bunch of gates (see page 2 of the data sheet)

it counts to 10 having one output (Q0-Q9) high for each step.

It's basically the same chip as the 4017B used here.

not that I'm reccomend that circuit (with a 9V supply) other than as an experiment as it's using the LEDS outside of their specifications and they may not last very long, it's better to use one resistor for each LED

--
?? 100% natural

Hi. So it's not a 4 digit counter, it's 10 digit counter, and that is why we see Q0 -Q9. But there is a 5 shift register in the IC.

Not sure what the code converter is about though.

At present what interests me is a decade counter.

From what I read, for each 7 segment display, you require 4 bits representing the count, and you are getting Binary Coded Decimal at Q1-Q4 (because we are using decade counters) and not regular binary (modulo 16?). So, when building for 7 segment displays you need 4 bits for every display. Therefore you would need a 16 bit counter (4 x 4 bit) to run four 7 segment LED displays. I guess so.

I mean 4 bit and 10 bit.

I've not enough knowledge yet to understand these counter IC's.

I've just started learning digital, and all I know about is 4 bit counters and how you can use those 4 bits (BCD in a decade counter) to run a 7 segment display (via a BCD decoder).

So, when I think about counters with 7 segment displays, I'm assuming your counter must be 4 bit, 8 bit, 12 bit etc.

I think this is true except for ring counters.

I just don't know why, with a decade counter, there are 10 bits in the IC MC14017B-D and not multiples of 4bits.

Am 30.6.2011 schrub Richard:

They just use different codes: the 4 bit counter outputs a base-2 code while the 10 bit counter outputs a 1-out-of-10 code:

base-2 1-out-of-10

0000 0000000001 0001 0000000010 0010 0000000100 0011 0000001000 0100 0000010000 0101 0000100000 0110 0001000000 0111 0010000000 1000 0100000000 1001 1000000000

The 1-out-of-10 counter could just as well be implemented using a base-2 BCD counter (e.g. an SN74LS160A) and a decoder (e.g. an SN74LS145).

Josef

--
These are my personal views and not those of Fujitsu Technology Solutions!
Josef Möllers (Pinguinpfleger bei FTS)
	If failure had no penalty success would not be a prize (T.  Pratchett)
Company Details: http://de.ts.fujitsu.com/imprint.html

Am 30.6.2011 schrub Richard:

It must be a decoder which outputs a special code, as a simple "BCD decoder" will output a 1-out-of-10 code. What you need is one that outputs a code geared towards 7-segment displays:

Input Output

0000 1110111 0001 0100100 0010 1011101 0011 1101101 0100 0101110 0101 1101011 0110 1111011 0111 0100101 1000 1111111 1001 1101111

The least significant bit of the output is the top horizontal bar, then the more significant bits are arranged from top to bottom and from left to right: 0

+-----+ | | |1 |2 | 3 | +-----+ | | |4 |5 | 6 | +-----+

Take a look at e.g. the 4511, the 7447 or any other "BCD to 7-segment decoder/driver".

It depends upon your display. You might want to count in octal, then a number of 3-bit counters is sufficient ;-)

Note that the integrated decodes/drivers also have a feature to suppress leading 0s.

Because the code it outputs is a 1-of-10 code.

Josef

--
These are my personal views and not those of Fujitsu Technology Solutions!
Josef Möllers (Pinguinpfleger bei FTS)
	If failure had no penalty success would not be a prize (T.  Pratchett)
Company Details: http://de.ts.fujitsu.com/imprint.html

Hi. Yes, the 4 bit counters that I am reading about are all binary counters. Even the decade (BCD) counter is, except that BCD in the whole sequence of bits are not binary.

And in this scheme I see how each display LED requires a Q1-Q4 output from a 4 bit counter.

So to display a count of 7953 we need four, 4 bit counters:

Q1-Q4 Q1-Q4 Q1-Q4 Q1-Q4 BCD sequence:......... 0111 1001 0101 0011

Decimal displayed:.......... 7 9 5 3

Output of 4 bit counter is base-2 code.

Not sure yet how you would get to display 7953 using the 10 bit counter. Whether in fact you would or could use 7 segment LED displays.

--
It's actually a 5 stage Johnson counter; a shift register is quite a
different animal.

--
It's actually more like a tricky 4 bit counter which only uses 10 of
the possible 16 output steps and presents them on the outputs one at a
time.

So to display a count of 7953 we need four, 4 bit counters:

....................... Q1-Q4 Q1-Q4 Q1-Q4 Q1-Q4 BCD sequence:.......... 0111 1001 0101 0011

Decimal displayed:..... 7 9 5 3 (on 7 segment LED)

Output of 4 bit counter is base-2 code.

--
Basically, how would you complete the above arrangement for this 10 bit 
counter:

....................... Q0 Q1 Q2 Q3 Q$ Q5 Q6 Q7 Q8 Q9

??? sequence:..........

Decimal displayed:..... 7      9      5    3
(on 7 segment LED)

So to display a count of 7953 we need four, 4 bit counters:

....................... Q1-Q4 Q1-Q4 Q1-Q4 Q1-Q4 BCD sequence:.......... 0111 1001 0101 0011

BCD decoder (to drive LED driver)

Decimal displayed:..... 7 9 5 3 (on four 7 segment LEDs)

Output of each 4 bit counter is base-2 code.

---

Basically, how would you make out a similar arrangement to the above for the 10 bit counter? What would it take to display 7953 on four seven segment display LEDs? How many counters?

....................... Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9

??? sequence:..........

??? decoder:..........

Decimal displayed:..... 7 9 5 3 (on four 7 segment LEDs)

Are we saying for 10 bit counter when the count reaches 7953 we have:

....................... Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9

1 in 10 sequence:...... X X X X

X = HIGH

1 in 10 decoder: (To drive LED driver)

Decimal displayed:..... 7 9 5 3 (on four 7 segment LEDs)

--
Almost.

Here's the difference between the counting patterns of decade and
binary counters outputs:

CLOCK  DECADE   BINARY 
        0UT      OUT

  0     0000     0000
  1     0001     0001
  2     0010     0010 
  3     0011     0011
  4     0100     0100
  5     0101     0101
  6     0110     0110
  7     0111     0111
  8     1000     1000
  9     1001     1001
 10     0000

--
You could, but you'd have to use a one out of ten to 7 segment
decoder.

Unobtainium, I think, unless you rolled your own.

--
That won't work; you'd have to use four 4017's and four "one out of
ten to 7 segment decoders".

Am 30.6.2011 schrub Richard:

Without some additional circuitry: you can't! The 1-of-10 code does not directly map to the 7 segments. You'd need a couple of OR gates: Segment 0 (the top most bar) is on if Q0 OR Q2 OR Q3 OR Q5 OR Q6 OR Q7 OR Q8 OR Q9 is on ...

The BCD to 7-segment decode/driver chips use a slightly more complex logic to determine which combination of the 4 bits causes which segment to light. It would be a nice exercise for Karnaugh-Veitch (sp?) diagrams!

Josef

--
These are my personal views and not those of Fujitsu Technology Solutions!
Josef Möllers (Pinguinpfleger bei FTS)
	If failure had no penalty success would not be a prize (T.  Pratchett)
Company Details: http://de.ts.fujitsu.com/imprint.html

--- Here: (View in Courier)

. DIGIT 4 . COUNT DECODE DISPLAY . +-----+ +------+ +-----+ . | Q9|---|IN9 g|---|g | . . . . . . . . . . . . . . . . . . . . . . | Q0|---|IN0 a|---|a | . +-----+ +------+ +-----+ . . DIGIT 3 . COUNT DECODE DISPLAY . +-----+ +------+ +-----+ . | Q9|---|IN9 g|---|g | . . . . . . . . . . . . . . . . . . . . . . | Q0|---|IN0 a|---|a | . +-----+ +------+ +-----+ . . DIGIT 2 . COUNT DECODE DISPLAY . +-----+ +------+ +-----+ . | Q9|---|IN9 g|---|g | . . . . . . . . . . . . . . . . . . . . . . | Q0|---|IN0 a|---|a | . +-----+ +------+ +-----+ . . DIGIT 1 . COUNT DECODE DISPLAY . +-----+ +------+ +-----+ . | Q9|---|IN9 g|---|g | . . . . . . . . . . . . . . . . . . . . . . | Q0|---|IN0 a|---|a | . +-----+ +------+ +-----+

The clocks into and the carries into/out of the counters aren't shown, but what happens is that as the count sequence progresses, the outputs which are hot get decoded so that the LED segments corresponding to the numerical values of those hot outputs are illuminated.

-- JF

Okay this is what I understand.

• Each display is a 7 segment LED, which, if you ignore DP has connections a-g. You obtain all the numerals from powering the seven LED segments in differing combinations.

• The above shows four 10 bit counters with outputs Q0-Q9. So, we are still using four ICs to show a count of 7953.

• In a 4 bit decade counter situation, each digit display is proceeded by a BCD decoder that takes a 4 bit input (Q1-Q4). If you look at the overall sitiation with the 4 bit situation, we have 16 bits lines that are decoded, (4 bits or wires for each display decoder, for each digit display).

• In the above situation each display decoder has 10 lines, taking input from Q0 to Q9. That requires 40 lines fed to the decoders in total.

• I thought that one, 10 bit counter might have been superior to a 4 bit counter, in terms of ICs required, but it is not. In fact, is the MC14017B really a 4 bit decade counter, but having 10 outputs (Q0-Q9)? That is what it looks like, but it's puzzling.

• I cannot understand why, when you can drive a digit display with 4 bits (only 4 bits required to get up to a count of 10), we have a decade counter with 10 bits.

• I'm obviously missing something.