A couple of simple questions about a simple op amp circuit

And, if you stop chopping up the messages, you'll know that the whole statement was about removing R5 from the circuit completely.

My how things can run a muck around here. Nothing but chop monkeys around here.

Jamie

Reply to
Jamie
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Well, I do enjoy Sam Adams however, I can not drink that any more. It seems to dry out my throat and gives me breathing problems when trying to sleep at night. You notice how I said at night, other times I just sleep at the desk! :)

Jamie

Reply to
Jamie

I had actually built a ckt very similar to this a while ago, without R4, R5, & C1. It "worked" very well, as far as keeping a load current fixed, as shown on a DVM. If I had thought to 'scope it I suppose that I would have seen oscillation. Next time I'll know.

Follow up question: if my ckt was oscillating, how would that affect the battery under test?

Well, that was embarrassing! When he said "U2", I thought that he was talking about the 2nd half of the op amp pkg. But the zener was clearly marked as "U2". I guess that I expected a "U" to be an IC & a zener to be a "D", never thinking ...

Thanks to all the reply-ers.

Bob

Reply to
Bob Engelhardt

You may have lucked out and not gotten oscillation. Depending on the op- amp and the FET, such a circuit may oscillate, it may be dead stable (not likely without a special op-amp), or it may just be laying in wait to surprise you.

Depending on how strong the oscillation is, the battery current may just have some ripple (not likely), it may be pulsed but retain the correct average current (this is kinda likely), or you may not be able to set the average current at all (most likely, but apparently not what you saw).

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Tim Wescott
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Reply to
Tim Wescott

I suspect he intended to replace the resistor with a conductor,

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Reply to
Jasen Betts

An equation,,, you mean like numbers?

My initial thought was that the capacitor in the negative feedback path is going to kill all the AC gain (because caps pass AC, and negative feedback reduces gain)

Looking closer I see that the op-amp is organised as an integrator integrating the difference between the voltage at the mosfet source and the voltage from the pot.

So, a step change at the source will result in a ramp at the op-amp output the slope is determined by (V_source-V_pot) R5 C1, this will result in a change that will turn the mosfet on or off the compensate for the error. As the source voltage approaches the set point the current in R5 reduces and the ramp levels out.

As I understand MOSFETs (which isn't all that well) that one is configured as a source follower, so it's going to have approxiately unity voltage gain.

So closing the loop the step response is going to be a logarythmic curve with the limit at the set point.

R5 is 1k and C1 is 10nF so the time constant is 10us whick looks to be between 10 and 100 times more than the time the op-amp takes to respond to its inputs, so it's going to mostly behave like an integrator and will quickly

The capacitances of the mostfet (which as I said I don't really understand) are all much smaller than C1, so I'm guessing that the mosfet will respond about 10 times faster than the integrator does.

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Reply to
Jasen Betts

No. An _equation_ describing the feedback loop from OpAmp output back to inverting input.

No.

...Jim Thompson

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| James E.Thompson, CTO                            |    mens     |
| Analog Innovations, Inc.                         |     et      |
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Reply to
Jim Thompson

R5, C1, and U1 form an integrator making the circuit a Type 1 system.

Reply to
Bob Penoyer

Perhaps. But that's not the whole story. How does the gm and Cgs of the FET affect the loop? ...Jim Thompson

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| James E.Thompson, CTO                            |    mens     |
| Analog Innovations, Inc.                         |     et      |
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Reply to
Jim Thompson

Well, as a quick look, I'd say gm isn't significant since Q1 is connected as a source follower.

Taking Ciss as Cgs, the IRF350's is about 2600pF. That and R4 form a time constant of 2.6us. R5 and C1 form a time constant (I know this is an odd way to consider an integrator) of 10us so the integrator is the dominantly slow function.

Going a step further, consider the entire loop: The integrator puts a pole at the origin; R4 and Cgs form a low-pass RC network that puts a pole on the negative real axis. So the root locus contains two poles, one at the origin and another to the left of the origin. Together, they describe a locus that is always in the left-half plane.

At least from this back-of-the-envelope approach, the circuit appears to be inherently stable.

Reply to
Bob Penoyer

The whole arrangement is to keep a direct capacitive load (to ground) away from the OpAmp, so it's a classic feed-around "lead" network.

But you're right, it appears to be stable without it... but I personally wouldn't try it that way :-)

I was trying to elicit someone actually doing the math, but that seems impossible now-a-days :-( ...Jim Thompson

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| James E.Thompson, CTO                            |    mens     |
| Analog Innovations, Inc.                         |     et      |
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Reply to
Jim Thompson

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