74LS193 Cascading Question

"Cascaded" as in hook the output of one into the input of the next, so the combined counting is increased.

You'd have to add logic to switch the count direction after the full count and when it gets down to zero.

Michael

Yeh, that's where I'm stuck. I've successfully cascaded all four chips to count up.....I can't figure out what circuitry I need to add. I know how to make them cascade count down but I have to manually switch wires to make it happen. I want it to automatically switch count directions when count is full and when count is zero. Bart Bart

Hi, Bart. Count up from 0000 to 9999, then reverse direction, counting down from 9999 to 0000. Rinse and repeat.

Not too difficult. I'd assume you've got all zeroes at the preset, and are using a power-up pulse to reset the count so you can start at zero.

Now set up an R-S FF with the Set condition being a count of 0000 (all four TCd active) OR the reset pulse. The Reset condition is the count of 9999 (all 4 TCu active). The R-S FF outputs can be ANDed with your clock to route the clock pulse to CPu or CPd.

Here's how it works. Your power up pulse sets the count at zero, and also sets the R-S FF so the counts will be routed to the Count Up input. After 9999 clocks, all four Terminal Count up outputs will be high, and are ANDed to the Reset input of tghe FF. That steers the next clock pulses to the Count Down input, and so on.

Look at the data sheet for details:

Of course, you've now got four LS193s, a flip-flop, and some combinational logic. You're now at the point where a PIC is more sensible solution.

Good luck Chris

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Something like this (view in fixed font or M$ Notepad):

| | To 4 ea. MR | ^ | | | TCd1 -| | __ | |__ RST-o-\\ \\ | TCd2 -| \\ | |-. | | )------/__/ | | TCd3 -|__/ | | | | | TCd4 -| | | | __ | | .----. .--| \\ | TCu1 -| | | | | | )- toCPu | |__ '-oS Qo-)--|__/ | TCu2 -| \\ | | | __ | | )--------------oR Q'o-)--| \\ | TCu3 -|__/ | | | | )- toCPd | | '----' o--|__/ | TCu4 -| | | | |COUNT ---------------------------' | | (created by AACircuit v1.28.6 beta 04/19/05

At count 0000, you have to AND all four of the TCd signals, and the same with the TCu signals at 9999. The RST is the power-up pulse you use to set initial count to 0000. Obviously that also sets the counters to up-counters.

Simple? Unfortunately, I guess you're at 7 ICs, plus whatever you want to do with the BCD outputs. Acres O' Digital.

Good luck Chris

Sorry -- the TCu and TCd are low on the last count, and go high as they roll over up and/or down. So, the two 4-input ANDs should be 4-input NORs.

Chris

put a flip flop on the last output pulse when it over flows. the Q's and !Q directly drive the direction of count.. this way it will simply reverse count when it hits the end. etc...

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"Bart" schreef in bericht news:9aeda$44d60d8d$d8442f66$ snipped-for-privacy@FUSE.NET...

Bart,

That 74LS193 are weird old things. You will have found that they are cascaded by connecting the carry output to upcount of the next chip and the borrow to the downcount. So this counters may by internally synchronous, all the rest is asynchronous. You will draw the same conclusion when you realise that the driving clock(s) are connected only to the first counter. To achieve your goal we'll have to open the toolbox of the old asynchronous designers with the suitable logic and a bunch more or less dirty tricks.

Mentioned by others already is the input circuit to switch up/down and lead the clock to the desired input. For your and mine convenience I draw it below. __ Setup -----| | __ |& |o-+-----| | +--|__| | |& |o---Cup | | +--|__| +--+ +-+ | \\ / | X | / \\ | +--+ +--+ | | __ | | +---| | | | __ |& |o-+-)--| | Setdown-----|__| | |& |o----Cdo +--|__| | | clock | --------------+ created by Andy´s ASCII-Circuit v1.24.140803 Beta

One 74LS00 will do the job. Remind that the trigger has active low inputs. So Setup and Setdown are normally high and you select by pulling the corresponding input low for a short time. Trying to set both at the same time will block the counter. You can't count up and down at the same time anyway.

To find a way to make the counter switch automatically, you'll have to look at the datasheet of the LS193. If you don't have it find it, download it and print it out. You can't do any serious work without it. The datasheets contains pulse diagrams. (At least mine - Texas - does.) You can see that, when counting up, the Carry appears just half a clockcycle before the counter rolls over. The first three counters in the row simply feed through the carry. It's on the trailing (rising) edge of that pulse of the fourth counter we want to act. That's to say the whole countercircuit should not roll over but counts down one step and switches to countdown mode. The latter can be achieved by presenting a short negative pulse to the Setdown. To count one down at the same time can be achieved by presenting 1111 1111

1111 1110 to the parallel load inputs and a short negative pulse to the Load input. Now that small negative going pulse can be made by a monostable. Half a LS221 will do the job. Use the positive edge trigger (B) input to connect the carry to and the inverted Q output to drive both Setdown and Load. The pulse length should be shorter then half a clock cycle but long enough to get the load done. One us (microsecond) will do. You may find glitches on the counter outputs which can be considered "normal" when you use asynchronous resets or loads. No need to say you'll need the datasheet of the 74LS221.

When counting down, the Borrow on the last LS193 appears when the counter reached all zeroes. We cannot do the load-trick as we have the parallel load inputs in use already, so we need something else. That else is another monostable, triggered on the rising edge of the borrow. This time we need the inverted Q output to trigger the Setup and the Q output to reset the counter as a whole. The disadvantage is that the all zeroes state resides twice the normal time, so two clockpulses.

You can overcome this disadvantage at the cost of some extra hardware and glitches but I consider this story long enough for the moment.

petrus bitbyter

Thanks so much for everyone's replies. Whew, I'm getting great info from you people. I've probably got every electronics book I could find from "Half Price Books" and also Googled till my eyes were bloodshot but this group has been critical to my successes on many projects. I simulated many configurations with cascading the 74LS193 up-down binary counters and hit on this design that does what I'd hoped.

I'll try and breadboard this first chance I get, I don't always trust simulators. Bart

Hi, Bart. A couple of notes on your circuit:

The '193 TCu output goes low when the chip reads a "9" ouput, and the clock is low. This means your logic will toggle when the most significant digit gets to "9" when it's counting up. Meaning your count up to count down transistion will go 898, 899, 900, 899, 898, &c. Also, since you're not using TCd on the last chip, it won't toggle until the digit gets to 9, which means an extra count, AFAICT. The count down to count up transistion will go 001, 000, 999, 000, 001, &c. So if you're going up to 999 instead of just 900, you might want to AND all the TC signals. And you should AND all the TCu signals together, as well as all the TCd signals to flip at 000 instead of 999. Again, read the data sheets. They tell all.

I don't see any provision to ensure that the output of the J-K FF will power up in the right state. Due to the perverse nature of inanimate objects, you should have a startup pulse to ensure it starts counting in the right direction. This startup pulse can also clear the '193 counters. You do want to power up with the initial count at 000, and the initial count direction being up.

Also, the LS76 is a bit of an odd beast -- if this is being used for high speed stuff, it's better to use something else if you're not sure about setup and hold times. It's sometimes better to avoid that IC unless you really know what you're doing, and need exactly what the chip provides.

But sometimes, it's best just to try things and see what happens. If your circuit doesn't do what you want, just reread the posts, look at the data sheets, and change a few things around. It's a good way to learn.

Good luck Chris

"Chris" wrote in message news: snipped-for-privacy@h48g2000cwc.googlegroups.com...

Thanks Chris, There were many flip-flops available in the simulator, I downloaded about every datasheet. D-style, J-K, 3-state, etc. and noticed distinctions such as leading edge, trailing edge, synch, asynch, etc. With my minimal background, all I figured was this would affect my max clock cycle time, and affect the transitions at full count and empty count. I wasn't worried about the additional clock pulses anywhere during the run, as long as every LED lit up in order and completed the full count both ways. I chose the 4071 F-F simply for its "toggle" feature. A more detailed explanation of my goal is to have a circuit that allows me to plug in any logic gate IC into a socket, then fire every combination of any/all pins, (except Vcc and Gnd which are powered separately) simultaneously monitoring all pins for outputs going HI. I've got several I/O circuit boards consisting of many I/O logic chips only. I've got one good board and several bad boards, all the chips are discontinued (old 15Vcc chips) and unidentifiable. My finished design will utilize an IC clip

instead of a socket and I'll place it on each chip on a board and run the design through its full counts, noting which pins output HI and what combination forced it HI. There are multiple occurrences of the same chips all over the board and I'm hoping this design will help me discover which ones are bad. Thanks for taking the time to read this and if anyone has further insights/comments they are more than welcome. Bart

J-K flip-flops can do amazing things, if the designer can figure out how to string them together properly. (i.e., you have to be smarter than the chip. ;-P )

Cheers! Rich