Ways to trigger a number of power transistors in sequence

Could some some electronics guru provide hints/suggestions. I have to trigger 16 power transistors in sequence, in round robin fashion. I am currently running SPICE simulations on a scaled down version consisting of 4 transistors. A pulse propagates down a serial in parallel out shift register. Each output is tied, via a resistor to the base od each transistor. So far, simulation results are encouraging.

What are other ways of achieving the same goal ? For example, if a i-4 multiplexer is used, how would one generate the enable sequence

00 -> 01 -> 10 -> 11 ? All suggestions are welcome. Thanks in advance.
Reply to
dakupoto
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Why not two cascaded decade counters with decoded outputs like the

74HC4017, driven from a clock? The master reset is active high and asynchronous so just send outputs 0-15 to your transistor driver circuit and tie output 16 from the second chip in the cascade to the master reset of the first.
Reply to
bitrex

A 4 bit counter and 16 channel mux like the 4067 is IMO the straight forward solution. Instead of a 4067 two 4051 will also do. If the power transistors are no MOSFETs or darlingtons you will need a buffer for the base current for each power transistor.

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Dipl.-Inform(FH) Peter Heitzer, peter.heitzer@rz.uni-regensburg.de
Reply to
Peter Heitzer

(you did not say frequency or if you have an external oscillator)

Use a CD4060 and a CD4514. The 4060 will give you the oscillator But if this is for a long term production product I'd find a different way. A micro controller with 16 GPIO pins would do everything you need. Or a little Microchip ATtiny25 with a 4 to 16 decoder.

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Chisolm 
Republic of Texas
Reply to
Joe Chisolm

If the OP's collector current requirements are modest enough (they also didn't define "power") they should remember this IC where you get 8 NPN Darlingtons in a single package, suitably clamped for driving mechanical relays etc:

Reply to
bitrex

snipped-for-privacy@gmail.com wrote on 7/7/2017 7:10 AM:

What you are asking is a bit like asking "how long is a piece of string?" Generating a sequence of pulses is a vague way to put it. What happens if there is some overlap in the pulses? What happens if there is no overlap in the pulses? Can you tolerate glitches in outputs that are not pulsing at that point? What is the time scale of the pulses?

Using a binary counter to drive a decoder can result in narrow spike pulses when the counter changes more than one output at a time. For example when the counter changes from 3 to 0 the decoder can see 1 or 2 as a very brief intermediate state and generate a spike on that output. There are several ways around that issue. One is to use the shift register you started with. You still have the issue of not controlling the overlap of the pulses but you won't get spikes on the other outputs.

Another approach is to use a Gray code for the counter where only a single output bit changes on any count. One form of Gray code is called a Johnson ring counter that is a shift register loop with an inverter in the loop. For example, with three bits you can generate six states; 000, 001, 011,

111, 110, 100 and back to 000. Decoding a state is a matter of detecting the edge of the transition between 0 and 1 using two input AND gates and inverters. There are many example circuits about.

Still, none of this controls the timing of the adjacent pulse edges. If you need to worry about the presence or absence of overlap of the pulse edges then you need to either use different circuits, or perhaps apply analog techniques to shape the pulse edges.

As others have indicated, a simple MCU can help with the issues of generating basic pulse sequences with or without overlap but may need to be augmented with analog circuits if you need fine pulse edge adjustments.

So how long a piece of string do you need?

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Rick C
Reply to
rickman

A ring counter ?

Reply to
jurb6006

I don't think any modern synchronous binary counter will do the former. There can be other more subtle timing problems but I don't think synchronously-clocked transmission gate "D" flip-flops will have major trouble with transient indeterminate states like a ripple counter would.

There will surely be some residual overlap and indeterminacy even with a synchronous counter as nothing truly happens at exactly the same instant in time when there are different delays involved, but it will be from the propagation delays and rise/fall times which are in the 10s or 100s of nanoseconds max for even 30 y/o CMOS and gee whiz how fast does this thing need to be?

Reply to
bitrex

Glitches is glitches... You'll have to tell me what acceptable values are. How long is *your* piece of string?

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Rick C
Reply to
rickman

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