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Verilog Vs. VHDL - What is the marted trends? What most of the professionals use today?

Hello all.

I have seen a lot of technical comprarisons about VHDL and Verilog. After reading those, I conclude that both VHDL and Verilog are ok and can make a good job, you just have to choose the one that beter suit your profile. I have to choose one of those languages to start learning this week, but I would like to know about not so technicals caracterist berore deciding.

I would like to know what the professionals use today. Wich one is more suported by EDA tools. I also would like to know about the trends of the market, if there are indicators that in the future Verilog or VHDL will be better suited for the job.

Please help me on this hard task of choosing what HDL to learn.

Thank you very much!

Uderman

Reply to
Uderman
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Either works, though I prefer VHDL by a long shot. You should learn what your customer/employer uses. If you're doing ASICs, that is likely VHDL if you're in Europe and Verilog in the US (though my PPOE used VHDL). FPGAs designers tend to use VHDL, even in the US. No idea why.

It's not at all a hard task. Pick one. Most of what you learn with one will transfer easily to the other.

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Reply to
krw

I think there is more free stuff available for VHDL. You should also learn PALASM so you can understand what the compiler is generating from the high level stuff.

Reply to
MooseFET

There's a vague generality that Verilog is more popular in Western North America and VHDL is more popular in the East. Personally, I use VHDL.

Best regards, Spehro Pefhany

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Reply to
Spehro Pefhany

About 7 years ago, when I first started working with VHLD, I received the impression that Verilog was more popular and was the "way of the future". Today, I get the impression that it the pendulum has swung the other way and VHDL is more popular.

Reply to
Noway2

Thank you all for the responses. I was more inclined to pick VHDL, and now even more. If anyone have other inputs I will apreciate that also.

Peace.

Felipe Uderman

Reply to
Uderman

I think both VHDL and Verilog suck. But somehow I'm finding VHDL more structured than Verilog. Verilog always reminds me of some obscure netlist format. I think both languas can get the job done. Be sure to learn and understand more difficult constructs so you can construct clever code which really uses the power of the HDL instead of writing a netlist by hand.

Try and search for 'priority encoder vhdl verilog' with Google. The stupid implementations consist of a bunch of if-statements. The clever ones use a for-loop and are just a few lines long.

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Reply to
Nico Coesel

That's about my take, having tried using both as a hobbyist. Verilog seems a little too terse to me and I prefer VHDL for its readability. I think someone experienced in Verilog would find it more readable, though. But I still consider Verilog more work on developing an acquired taste for it than VHDL requires. I found VHDL something I could immediately get the hang of, while Verilog made me stop and remember things a little more often.

However, I'm not deep enough into either one (I don't do ASIC design and only use VHDL for FPGAs) and/or the compilers that exist today to know if there are any specific benefits (I am imagining here something like the benefit of FORTRAN over C for some compilations because FORTRAN makes useful guarantees about passed parameters that C does NOT make and compilers can take advantage of this knowledge.) I don't think there is, but I could easily be wrong about that.

Jon

Reply to
Jonathan Kirwan

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