VERILOG and VHDL

My favourite book that covers both Verilog and VHDL is 'HDL Chip Design' by Douglas J. Smith.

You'll have to contact the Xilinx or Altera people for the cost of a dev kit where you are.

The design flows in the Altera and Xilinx tools are somewhat different, but independent of the HDL language used. You can get the development environment (mostly) free on the web from both vendors.

Cheers

PeteS

You do not need to know Verilog or VHDL or indeed any other textual HDL to implement designs in FPGA's or CPLD's.

Personally I find they get in the way of producing high speed complex bug free designs.

I design highly complex image processing/camera/video systems using nothing more than schematic capture and a hierarchical design structure.

This provides designs that are highly modular, self documenting and easily understood and modified years later by other engineers.

Slurp

Depends on what you are designing. Complex logic is terrible to maintain when contained in a schematic. The same goes for showing the design hierarchical overview in HDL. My designs are mostly hybrid. Schematics to connect the blocks and do simple counter / buffer stuff, HDL for complex statemachines. And some documentation ofcourse.

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Nonsense. VHDL and Verilog are used industry wide for such things. Apparently it's only you who has this problem.

...and you can't do this in a HDL? At one time I thought like you, but then I grew up. Schematics might be great for dataflow and analog circuits, but they suck for any complex logic.

Nonsense again. VHDL is quite easy to make self-documenting. My guess is that you've never really tried to change tools. I have, and I'll not go back, willingly.

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  Keith

Nowhere did I say VHDL and Verilog is not the norm - just that it really is not necessary if you know what you are doing and want to get the job done. I don't consider I have a problem at all, I can get to a solution before anyone else using a HDL.

Didn't say I couldn't ( you seem to be very defensive!) . I can write Verilog - does not get to the solution very quick, easy to intoduce bugs and very hard to find your way round hundreds of pages of script. A picture is worth a thousand words. If you create or use megafunctions you really do not need to be involved with gate level logic - I guess graphical languages have moved on since you last looked!

Horses for courses - you carry on your way and I will carry on mine - I certainly don't have a problem with that.

Slurp

You must do some pretty simple stuff. Try designing a processor using only schematics. It was done thirty years ago. It is no longer. I wonder why?

Defensive, nope. I'm on the offense. Defense is for wussies. ;-)

You must be very poor at it.

Nope. A well done hierarchical design in a HDL is quite easy to read. Complex state machines are a piece of cake.

I think you're shortchanging yourself. Like I said, I once resisted VHDL (and even had another engineer do the designs from my specs). No longer.

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  Keith

One module (out of around 68) of a recent Altera Stratix II design was a 32 bit RISC processor designed from scratch and verified in less than 2 weeks. The compiler took another 2 weeks to write. All designed using hierarchical schematics. The whole project has taken me single handed less than 6 months.

If that is simple stuff then I take my hat off to you.

On the contrary.

...... as are they using a graphical approach.

Experiance and results say not.

I expected a Holy War [tm], but not necessarily over the schematic/HDL issue ;)

FWIW, when I do FPGAs, I do them exclusively in HDL. I personally find it much simpler to deal with than a schematic, although I am perfectly at home in schematics (I had better be ;)

I had quite a learning curve to get to this, but once I got comfortable with HDL [some years ago now] , I personally won't look back - a description of a part in Verilog or VHDL tells me more (imo) about the part than any pure schematic symbol ever could. Interestingly, one of the reasons I started learning HDL was because I had to write some programs to implement a bunch of boundary scan tests, and BSDL is a subset of VHDL. I chose to learn BSDL as it is integral to really understanding JTAG tests.

There are those who see it differently, of course.

Cheers

PeteS

I agree, but we are in the minority. I find that my schematic-based designs are simpler, faster, and far less prone to bugs as compared to things that HDL designers do. HDLs are good for some things like tables and address decoders, just wrapped in a box and properly commented.

I greatly prefer flipping through, say, 30 pages of nicely commented schematics as compared to, say, 5000 lines of cryptic, uncommented VHDL.

All my FPGA schematics begin with a block diagram, a table of contents, and timing diagrams.

John

Eureka! - A like minded professional at last! As you say John, we are very much in the minority!

May be it is just the way our brains are wired.

Slurp

True.

OK; hopefully you realize this is not true for everyone.

All the contemporary Verilog/VHDL "suites" (e.g., ActiveHDL, ModelSim, etc.) support a mixed schematic entry/VHDL/Verilog design style. IMO, that is the best of both worlds... use an HDL for fancy behavioral logic like state machines, use schematics to visually "tie together" the various levels of the hierarchy... and then use whichever you prefer for the complex/high-speed parts.

---Joel

Can you recommend an idiot level (me) schematic/fpga system, as I want to convert some ttl/cmos circuits to a single lump, memory address counters and glue logic etc.

I've looked at the Xlinx site, and I couldnt even figure out what breed I wanted. I'm downloading one of their demos at the moment

martin

If you download the Altera Quartus web edition from

(you need to obtain a free license file) - one of the included libraries actually holds 74 series functions, eg in the schematic editor if you double click on the schematic page, enter "7490" or whatever - up pops the appropriate symbol and underlying logic. For more sophisticated counters (up to 256 bits) enter "LPM_COUNTER" and you are presented with an easy to use multipage wizard to set up your counter configuration, and an appropriate symbol is dropped on the schematic when you finalize the wizard.

HTH

Slurp

Wow, thanks for that, brilliant [insert ASCII for thumbs up here]

martin

..... forgot to add that for your application I recommend you look at the Altera MAX II range of CPLD's. A CPLD has on board non -volatile configuration memory which means the programmed device is 'stand alone' .

If you use an FPGA you will need external NV memory - normally Flash, and some kind of boot loader. Altera do produce chips which have both the Flash and boot loader integrated in one device but these work out much more expensive than a 'roll your own' CPLD based loader and separate Flash.

Another plus is that the CPLD's are much cheaper than an FPGA - a smallish MAX II part of the order £2 - £3 will typically hold the equivalent of

50 - 75 MSI 74series logic functions with ease.

Slurp

The Xilinx schematic library also has a lot of 74xx TTL blocks, plus a lot of general-purpose latches and counters and gates and stuff.

You can grossly waste resources here, like using three outputs of a

1:16 decoder, or five bits of an 8-bit latch; the compiler will strip out the stuff that's not actively used.

John

Of course. Not everybody can produce high-speed, complex, bug-free designs.

John