I am designing a circuit to monitor Vds (0 to 4.0V) during "on" time of high side FETs. The Si-C diodes (D1,2) are not sharing equal current in this circuit; will they allow +/-3% reading accuracy? What else have I missed?
Tanks,
Harry
Den tirsdag den 18. november 2014 23.28.24 UTC+1 skrev Harry D:
it isn't very clear from the datasheet but it looks like Vf changes ~100mV/100mA
3% of 4V is 120mVyou can skip the switch if you use the gate drive as "pullup"
-Lasse
Would love to help you however, your link provides no image or schematic to look at, just a blank sketch pad, if that is what you want to call it?
But, diodes in general do not share the same parallel paths that well. The one with the lowest Vf will go first.
Ballast resistor per diode may help.
Jamie
Den tirsdag den 18. november 2014 23.28.24 UTC+1 skrev Harry D:
it isn't very clear from the datasheet but it looks like Vf changes ~100mV/100mA
3% of 4V is 120mVyou can skip the switch if you use the gate drive as "pullup"
-Lasse So you say, remove U1 and drive R1 with the gate drive clamped instead of
5V? That would simplify things but still have the D1,2 current unbalance.Harry
Den onsdag den 19. november 2014 00.25.24 UTC+1 skrev Harry D:
yes you could do that.
the unbalance will still be there but at 100mV/100mA and you use ~1mA I don't see that making much difference. The difference between the diodes will probably be more
-Lasse
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