Hi,
I am working on a prototype PLL, and before implementing it in ASIC CMOS technology I would like to build one using off-the-shlef components. A VCO can easily be found in analog PLLs, with tuning voltage input. I also need a classical Charge pump with up, down inputs. Do you know any commercial chips providing such a functionality?
Kind Regards.
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Not that I know of. And I'm the one who coined that phrase... in the mid '60's :-)
I do them all the time on custom chips.
You might be able to do it with 4000 series CMOS, but it'd probably not be fast enough. For instance you can access the phase-detector - charge-pump combo in the '4046, BUT you can't control current like I suspect you want to do. ...Jim Thompson
--
| James E.Thompson, CTO | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| Phoenix, Arizona 85048 Skype: Contacts Only | |
| Voice:(480)460-2350 Fax: Available upon request | Brass Rat |
| E-mail Icon at http://www.analog-innovations.com | 1962 |
I love to cook with wine. Sometimes I even put it in the food.
One method would be to use an HC4046 and a dual comparator. Bias the
4046 PD2 output at mid-supply with a couple of resistors, feed it into one input of each comparator, and bias the other inputs at 0.25 and 0.75 times VDD. That'll give you hard up/down outputs.Cheers
Phil Hobbs
-- Dr Philip C D Hobbs Principal ElectroOptical Innovations 55 Orchard Rd Briarcliff Manor NY 10510 845-480-2058 email: hobbs (atsign) electrooptical (period) net http://electrooptical.net
"Hard" up-down is already there in the 'HC4046. The OP probably wants switching current sources and sinks. ...Jim Thompson
--
| James E.Thompson, CTO | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| Phoenix, Arizona 85048 Skype: Contacts Only | |
| Voice:(480)460-2350 Fax: Available upon request | Brass Rat |
| E-mail Icon at http://www.analog-innovations.com | 1962 |
I love to cook with wine. Sometimes I even put it in the food.
I like this one,
ftp://jjlarkin.lmi.net/V346_phase_det.jpg
external to an FPGA. The FPGA pins are always-on hard logic drivers, so their pullup/down strength and tristate behavior don't matter.
This can be made to have zero deadband, if the phase detector in the FPGA is done right.
John
Only one output though. For current sourcing/sinking, replace the dual comparator with an LM13700.
Cheers
Phil Hobbs
-- Dr Philip C D Hobbs Principal ElectroOptical Innovations 55 Orchard Rd Briarcliff Manor NY 10510 845-480-2058 email: hobbs (atsign) electrooptical (period) net http://electrooptical.net
CMOS
VCO
need
commercial
-- Yes, this is what I need. http://img64.imageshack.us/img64/3196/16254682.jpg Inputs will be 10 ns pulses, about 10-20 MHz in frequency. So it looks like I will need to build the charge pump using current sources (20uA - 500uA tuning) and analog switches. Besides a bootstrap buffer wouldn't be bad, and some compensation of current mismatch (source - sink). Do you have any suggestions building such circuit? :-) Peter S. --------------------------------------- Posted through http://www.Electronics-Related.com
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