Transmission line emulation.

Works for me. The cylindrical symmetry isn't very relevant either, at that aspect ratio; I use it unrolled, where it's more properly called parallel-plate transmission line, usually made with PCB layers, or copper foil tape which is flexible and easy to shape (for prototyping purposes, of course).

The real trouble is that, making connections to it takes a lot of space (at least the width of the TL, obviously), and hence adds ESL (or more correctly, some kind of tapered or higher-Z TL section, which exhibits low frequency equivalent L).

Tim

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Gee it would have been nice if Clive had told us the impedance to begin with. So as a model two sheets of aluminized mylar? I guess that will be hard to solder to without melting the mylar. I don't see your problem with the ends. Certainly there will be an end effect.. but I assume the thing is much longer than it is wide, so that should mostly go away. (Or are you seeing some problem I'm missing? )

George h.

Absolutely not, John. There've been some genuinely useful responses among the rote this-is-the-way-I-was-taught stuff, for which I'm genuinely grateful. There are large gaps in my knowledge which I try to fill as needed, and the experience of others is often invaluable.

In an ideal world, we could all reveal everything and contribute co-operatively. But that's jus' goddam' pinko talk.

Cheers

We can't always reveal a lot, and that's not news. Can be a pain yes, but tis life.

NT

You could describe the geometry and maybe the materials and length of your transmission lines without revealing any great secrets.

se, the

Hmm I think that's wrong. By sharing what little knowledge I have with SED. (or elsewhere) and getting back in kind, I multiply my wisdom by ~N (number of SED who can help) (lotsa times it only takes one good reply to put my brain on a better path.)

George H. who has never seen an NDA.

Lots of semiconductor vendors now want a signed NDA before they will send you a data sheet.

We got some orders from a biggish company that first insisted on a mutual NDA. Then they decided to design the gear themselves. Too bad! They had to buy the design concepts from us.

thing is much longer than it is wide, so that should mostly go away. (Or are you seeing some problem I'm missing? )

Well, it is in the things I work with (e.g., switching supplies, where the TL length is comparable to its width).

Tim

====snip====

Just for the record; None.

Gawd help us!

Yes, the line is continuously loaded with inductance (it's in the nature of any current pathway). You could simulate it with a series of hundreds of very tiny discrete inductances per metre of simulated line to a reasonable standard of accuracy. The point to remember is that you only get mutual inductance with parallel current pathways and none of these discrete inductances run parallel to each other in a real cable, which means you can't cheat by modelling it with a tapped inductor.

This might be useful to someone.

Version 4 SHEET 1 880 680 WIRE 80 128 16 128 WIRE 128 128 80 128 WIRE 272 128 208 128 WIRE 368 128 272 128 WIRE 576 128 464 128 WIRE 656 128 576 128 WIRE 16 160 16 128 WIRE 368 160 320 160 WIRE 512 160 464 160 WIRE 656 176 656 128 WIRE 320 192 320 160 WIRE 512 192 512 160 WIRE 16 272 16 240 WIRE 656 304 656 256 FLAG 320 192 0 FLAG 512 192 0 FLAG 16 272 0 FLAG 656 304 0 FLAG 80 128 GEN FLAG 272 128 A FLAG 576 128 B SYMBOL ltline 416 144 R0 WINDOW 0 2 54 Bottom 2 WINDOW 3 6 60 Top 2 SYMATTR InstName O1 SYMATTR Value PCB1 SYMBOL voltage 16 144 R0 WINDOW 0 -86 50 Left 2 WINDOW 3 -319 88 Left 2 WINDOW 123 0 0 Left 0 WINDOW 39 0 0 Left 0 SYMATTR InstName V1 SYMATTR Value PULSE(0 1 1n 5p 5p 500p) SYMBOL res 112 144 R270 WINDOW 0 -36 59 VTop 2 WINDOW 3 -40 59 VBottom 2 SYMATTR InstName R1 SYMATTR Value 50 SYMBOL res 640 160 R0 WINDOW 0 -53 45 Left 2 WINDOW 3 -50 72 Left 2 SYMATTR InstName R2 SYMATTR Value 50 TEXT 56 400 Left 2 !.model PCB1 LTRA(len=10 R=100m L=7.8n C=3.12p) TEXT 208 448 Left 2 !.tran 0 5n 0 1p TEXT 112 296 Left 2 ;Lossy PCB Trace JL May 4, 2019 TEXT 152 344 Left 2 ;50 ohms FR4 microstrip TEXT -296 328 Left 2 ;w=37 diel= 20 mils TEXT -296 360 Left 2 ;L = 7.8 nH/in C = 3.12 pF/in TEXT -296 392 Left 2 ;delay = 156 ps/in TEXT -296 296 Left 2 ;'len' is inches TEXT -296 424 Left 2 ;DCR ~~ 15 mR/in

The LTRA series resistance is actually skin effect, so the R=100m is a wild and inaccurate guess. I might TDR some test cases and refine the model.

I'll have two edge-launch SMA connectors about 0.7" apart, with a u-shaped 50 ohm trace between them, and a signal pickoff somewhere, probably midway. I want to modify the trace or the ground plane or something to compensate for the lumped capacitance of the pickoff. I can sort of Spice that.