Thermal resistance through the top of an SO-8

If the bottom tab is properly heat sunk, you might improve things a tiny bit by sinking the top too. But if the tab is soldered to a PCB that is mediocre thermally, the top sink could help a lot.

I'd extend the topside power pour and solder down a surface-mount heat sink over the part. Best of both worlds, and easy to assemble.

If there's any air flow, that kind of sink will help a lot, and not add much capacitance.

One might use that same sink and add some gap-gunk on top too, but I can't estimate how much that might help. It would help hot-spot heat spreading on a regular SO8, but that Vishay package probably does the spreading well already.

I guess the heat sink could be *not* connected to the tab, but just gap-padded to the top of the part. That would be feasible but obscure.

We have epoxied pin-fin sinks to FPGAs and measured substantial cooling (using a calibrated ring oscillator) but the improvement was as much from hot-spot spreading as actual heat dissipation.

This thermal stuff is hard. The best analysis is usually an experiment.

Ohh, I discovered Vishay's TOP-SIDE cooling parts! Yeah, Siliconix engineers! E.g., SiDR140DP rated 100A, only 0.56mm thick, 0.8 C/W to top metal pad.

then there's also Infineons DirectFETs

Yes, I'd not considered them, my application requires very low Rds(on), in the past they've been too high, too expensive. But I found: BSB008NE2LX, 0.8 m-ohms, only $1.13 qty 1k. Infineon also calls this CanPAK. Hmm, the SiDR140DP claims 0.67 m-ohms. Nice choices.

One square of 1 oz copper, if it's actually 1 oz, is about 0.55 mohms, so it can be hard to use a sub-milliohm fet. Sometimes I use several smaller parts in parallel.

Goal: efficient low-voltage high-current boost converter.

First, actual Rds(on) is of course a bit higher due to current and temperature multipliers. I'll be using many FETs (many dozens) in parallel, but will expect each one to have a low Vdrop at moderately-high currents. Traces will be wider than long, and Yes, I'll be using 3 or 4-mil copper, and on both sides for some paths. Each FET will drive its own low-Ron inductor, lots of good choices. Want to be using big copper bus bars as much as possible. It's likely that each FET will only dissipate a few watts.

OK, that sounds like fun.

Going to use real bus bars? Bolted or soldered?

Imagine three parallel bus bars, copper or aluminum, tapped. Bolt a lot of small booster PC boards across the bus bars.

Dunno about Vishay, but some mfgs (TI in particular?) have been introducing "thermal characterization" parameters, which are direct or indirect C/W figures to useful points. Such as the typical temp drop through the top, when mostly the leads are sinking heat (this corrects for the convection and conduction cooling to the top, where your thermocouple touches it, relative to the junction temperature you actually want to measure), or the actual thermal conductivity through the top (give or take conduction elsewhere).

One might infer, to various degrees of reasonableness, that other manufacturers use similar internal geometry and encapsulant, and therefore the figures should be similar... :-)

Tim