The Future of Computing

What do people think of the possibility in the distant future of transitioning to a solid 3d block silicon IC structure?

Thermal management is the most obvious issue. Extremely low power circuitry exists, albeit slow. Coper rods could be included to improve heat transfer to the surface.

NT

Reply to
tabbypurr
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I expect most supercomputers for the forseeable future to look pretty much like they have hypercube connectivity.

Domestic and office PCs have reached a limit where they are already more than powerful enough so the next stage is to do the same with a bit less power and less silicon (or a cheaper alternative).

Better interfaces between modern SSD type memory and human brains looks like it might happen in the reasonably forseeable future.

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I think their schedule is a little optimistic. YMMV

Too difficult to engineer. Self assembling chemical semiconductors could be one way that things might go or even subverting DNA replication to solve certain types of hard combinatorial problems.

The other possibility gaining credence is exotic chemical systems in 3D printed shaped chambers to solve specific problems at first or even general purpose computing one day.

At the moment they are still at the level of basic gate components:

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A fully working liquid chemistry computer would be impressive.

--
Regards, 
Martin Brown
Reply to
Martin Brown

Diamond is better, and tolerably easy to lay down by chemical vapour deposition.

Don't forget Josephson junctions - which seem to be available with high temperature superconductors.

--
Bill Sloman, Sydney
Reply to
bill.sloman

The problem is yield. Bonding known-good dice to known-good chips on wafers is barely acceptable, and iterating the process to make real 3D is very hard.

You can't mix front-end-of-line (FEOL) processes (the ones that make the actual transistors) with back-end-of-line (BEOL) ones (basically wiring) because you need things like 900C anneals and 600C epitaxy, whereas FEOL stuff is typically limited to 300C. That means that you have to stack thinned-down 2D structures.

Then there's the elevator shaft problem. The reason that tall buildings have "sky lobbies" is that if all elevators go to all floors, eventually all your floor space is taken up by elevator shafts. The same applies to the through-silicon vias (TSVs) that you need to go from layer to layer.

So fairly flat 3D structures are reasonable, but anything with the aspect ratio of a cube isn't.

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs 
Principal Consultant 
ElectroOptical Innovations LLC 
Optics, Electro-optics, Photonics, Analog Electronics 

160 North State Road #203 
Briarcliff Manor NY 10510 

hobbs at electrooptical dot net 
http://electrooptical.net
Reply to
Phil Hobbs

Yield could I expect be addressed with a self test routine that permanently disables all faulty blocks. Or where practical limits what they can do to what works.

I'll look at that later, must run.

Surely a 3d block gives better interconnectivity than today's flat plane devices.

NT

Reply to
tabbypurr

A key problem with today's advanced small-geometry processes is getting the heat away from the junctions.

Proposed new structures have to have a story for how that is achieved.

Reply to
Tom Gardner

Is FEOL done first?, then you mean that BEOL is limited to 300C. (not that it matters here.)

George H.

Reply to
George Herold

Right, fat fingers.

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs 
Principal Consultant 
ElectroOptical Innovations LLC 
Optics, Electro-optics, Photonics, Analog Electronics 

160 North State Road #203 
Briarcliff Manor NY 10510 

hobbs at electrooptical dot net 
http://electrooptical.net
Reply to
Phil Hobbs

There are some stacked-wafer 3D technologies, but they are better suited to memory than to computing. CPUs get too hot.

Silicon may finally flatline at 5 nm, maybe 10x the performance that we have now.

Most people are happy with a 1 GHz ARM and some flash in their smartphone. Disk drives are in the terabytes and the cloud stores a lot of our stuff. We don't really need a lot more computing.

The "grand problems", weather and fluid flow and some math things, wouldn't be greatly benefitted by 1000 or even 1e6 times more supercomputer power than we have now.

I would like 100x more Spice power, but that could be done any time by adapting LT Spice to use an Nvidia card.

--

John Larkin         Highland Technology, Inc 

lunatic fringe electronics
Reply to
John Larkin

I'd settle for having stepped simulations run concurrently on separate cores.

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs 
Principal Consultant 
ElectroOptical Innovations LLC 
Optics, Electro-optics, Photonics, Analog Electronics 

160 North State Road #203 
Briarcliff Manor NY 10510 

hobbs at electrooptical dot net 
http://electrooptical.net
Reply to
Phil Hobbs

Heat production has to be orders of magnitude less. I see no other practical-ish option.

NT

Reply to
tabbypurr

There are CPUs that run cold today. Minimal power use is an absolute necessity if your silicon's an inch thick.

We so do, but I'll leave that discussion for another day.

We must have very different ideas of what the grand problems are. But I don't want to diverge into yet another topic for now.

NT

Reply to
tabbypurr

That is where my knowledge runs right out. What prevents one from, in principle, writing aluminium tracks using a scanning atom beam, then exposing it to low temperature gas to passivate it? Could data be piped round by SiC LEDs?

NT

Reply to
tabbypurr

Aluminum is useless because of electromigration, and besides it melts at about 700C. You can't push much more than 1E6 A/cm**2 even through copper. (That sounds like a lot, but it's a serious limitation.)

And then there are the dielectrics.

But the main issue is diffusion of metal impurities, which trashes the carrier lifetime.

Could data be

Way too slow, and wrong wavelength. For silicon photonics you want InGaAs or InP.

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs 
Principal Consultant 
ElectroOptical Innovations LLC 
Optics, Electro-optics, Photonics, Analog Electronics 

160 North State Road #203 
Briarcliff Manor NY 10510 

hobbs at electrooptical dot net 
http://electrooptical.net
Reply to
Phil Hobbs

But all the device scaling is taking us the opposite direction, even at fixed clock rates. At this point, smaller transistors are leakier, slower, and have less gain. It's been that way since about 65 nm.

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs 
Principal Consultant 
ElectroOptical Innovations LLC 
Optics, Electro-optics, Photonics, Analog Electronics 

160 North State Road #203 
Briarcliff Manor NY 10510 

hobbs at electrooptical dot net 
http://electrooptical.net
Reply to
Phil Hobbs

Add TEGs to the periphery and power the device by the escaping heat.... lol

It might be feasible to capture some of the waste heat this way to reduce the power input. While not reducing the need for cooling the device, it can help with the total energy in and waste heat to the environment.

--

Rick C
Reply to
rickman

I'd be happy if my PC would just do the normal PC stuff without bogging down. I don't know that CPU speed affects many uses of computers other than the small percentage of uses that basically need an SR-71 sort of CPU. Even gaming computers aren't suffering from CPU performance. Often the limitations are elsewhere.

But then Bill Gates is supposed to wonder why anyone would need more than 640 kB of memory. Seems like every MIP finds a home.

--

Rick C
Reply to
rickman

I want sliders so I can tune values and see the resulting waveforms essentially instantly. OK, 1000x.

--

John Larkin         Highland Technology, Inc 
picosecond timing   precision measurement  

jlarkin att highlandtechnology dott com 
http://www.highlandtechnology.com
Reply to
John Larkin

I'm guessing the TEG would add to the thermal resistance, making the IC run hotter. (TANSTAAFL)

GH

Reply to
George Herold

Well, you can get the first factor of two by mounting solder-bump devices back to back on double-sided circuit board. The problem, though, is the cost of making a new layer of single-crystal silicon, which gets extremely difficult if it has to go over a road system of wiring. Most ICs are monolithic (start with a chunk of pure silicon) and only small bits of noncritical (polysilicon) material ever get deposited on top.

The Samsung stacked-elements flash chips that are in SSDs nowadays are multistory stacks of elements, but that works for flash because there's very little heat dissipated (addressing one word, you leave millions of others un-powered). And, it relies on doing LOTS of mechanical assembly work. The robotic wire-bond machines must spend a lot of time connecting the layers.

Reply to
whit3rd

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