testing an ADC

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We have a product with a 12-bit ADC that's being clocked around 60
MHz, with the data poured into an FPGA. We want to do a good
production test.

We can route a big triangle wave into the adc and take a lot of
samples. Our thinking is that each bit should be high about 50% of the
time, and we can set limits on that. This will catch bits stuck high
or low, bits shorted to other bits, opens, logic races, and general
misbehavior.

We already have a "logic analyzer" in the FPGA. It snapshots 1024 ADC
samples and some other states in a big RAM. We could read that out
(many times) and analyze each bit in our Python test program, but that
would be slow. So the kids added 13 new 32-bit registers: total sample
count, and one register per ADC bit to total up how many 1's that bit
had. Now we can get 60 million coin tosses per bit line, in one
second, and read that out over ethernet in a millisecond.

Turns out that 60 million coin tosses has some pretty powerful
statistical behavior. The probability of heads being outside 49..51%
is effectively zero.




--  

John Larkin         Highland Technology, Inc

lunatic fringe electronics  


Re: testing an ADC
On 4/18/19 10:04 AM, John Larkin wrote:
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Probably won't catch out-of-spec DNL though.  You'd want to look  
carefully at the major carry etc.

Cheers

Phil Hobbs


--  
Dr Philip C D Hobbs
Principal Consultant
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Re: testing an ADC

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  Something seems very wrong with his statement.  It says more about  
his code than it does about stats.

  There needs to be a true rng somewhere in this.

  Bad code can 'ring' good or bad exactly 50% of the time or very  
close to it.

  A cool test would be to arrange for 60 million folks around the  
world to sign up to perform a single coin toss at a specific moment  
in time, and then record the results, and have a website database  
set up to tally up the result reports.  One could even make a  
distribution graphic of the globe showing it as a perfectly  
homogenized aggregate or have patches.

  I say perfect aggregate, but not exactly a 50 50 result  
distribution.

Re: testing an ADC
John Larkin wrote...
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 You want to test the ADC better than the manufacturer?


--  
 Thanks,
    - Win

Re: testing an ADC
On 18 Apr 2019 07:23:37 -0700, Winfield Hill

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Unfortunately the beautiful stats will be wrecked by the actual ADC.
It will be interesting to see what a few ADCs really do.  

We mostly want to catch possible opens and shorts on production
boards, but we'd spot the rare bad ADC too. 32 bits and 60 million
samples are gross overkill, but it's free.

We will also analyze the saved 12-bit ADC codes to check gain and
offset.

We try to have production test catch any possible assembly error, not
just functionality and specs.


--  

John Larkin         Highland Technology, Inc

lunatic fringe electronics  


Re: testing an ADC
John Larkin wrote...
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 OK, John, you gotta tell us the part number.


--  
 Thanks,
    - Win

Re: testing an ADC
On 18 Apr 2019 08:02:16 -0700, Winfield Hill

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Do I have to?

We're going to try this soon on a board with a 10-bit part, ADC10080,
at 60 MHz. The more serious application will use a 12-bit ADC at 40
MHz. We haven't picked that ADC yet. The customer insists on running
our proposed BOM through their two expensive and mostly useless EOL
research services, and we can't finalize the design until they do
that.

The FPGA on the existing board is a 7020 ZYNQ.


--  

John Larkin         Highland Technology, Inc
picosecond timing   precision measurement  

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Re: testing an ADC
On Thursday, April 18, 2019 at 7:05:02 AM UTC-7, John Larkin wrote:
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Test, but for what?   Will you calibrate the reference voltage?   Do
a few cycles overclocked to a 20% higher frequency?  Clock the
gizmo asynchronously to the other logic and examine for
crosstalk?

Slow triangle-wave input is OK for missing-codes errors, but
those only happen in some kinds of converters.   Can you close
the loop (do D-to-A) and production-test by X-Y of input and
output on an o-scope?   Square-wave input and test for slewing?

Re: testing an ADC
wrote:

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Bits stuck high, stuck low, shorted to other bits, open, generally not
behaving. This is for production testing.




--  

John Larkin         Highland Technology, Inc
picosecond timing   precision measurement  

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