TCXO (shopping for replacement)

Thanks for the reply. No wonder I was having so much trouble:)

A quadrature PLL wouldn't help John much. It's for phase noise measurements which doesn't measure the slow frequency drift he is after. Here's an example:

Low-Cost Phase Noise Measurement

What John needs might be a DMTD (Dual Mixer Time Difference) circuit. For example, "A Small Dual Mixer Time Difference (DMTD) Clock Measuring System" by W.J. Riley, Hamilton Technical Services:

It has a has a resolution of 20 femtoseconds for a 10 Hz beat frequency at an input RF frequency of 10 MHz. You can't measure that on a scope.

The LT1028 amplifier afer the mixer (U4, Mixer Module, page 6) can be improved to reduce the input noise.

Along with the DMTD, you might wish to get the analysis program, Stable32. It is available at

I think I paid something like $300. Absolutely essential for these kinds of measurements.

There are many articles available on Allan Deviation, far too many to list here.

I don't know what would happen if John wants to gate the oscillator. But since it is a crystal, the slow startup would be a problem, so I don't think that is an issue.

I checked. It was probably $395.

The DMTD is a fairly easy build, subject to low level crosstalk, grounding, bypassing and cable issues. But it is worth it.

With three inputs, you can tell which oscillator is the most stable, and by how much. You can then use it to grade other oscillators and figure out which ones are the best quality.

I have the software to do this and more info somewhere among 526,390 files on my SSD's. If anyone is interested, I will see if I can find it.

I should mention also that a phase noise tester is also needed to measure the rms jitter in an oscillator. The Wenzel is very basic and only a start to the problem. More info is available online and in the Time-Nuts archives:

We think in time domain. We have a new test set that measures time and jitter by comparing one time delay to another using a d-type flipflop. Our jitter floor is in the 10s of fs.

The jitter there included the stuff that made the swept test signals, so the flop itself must be considerably better. Could have used a micrometer-drive trombone or a varicap-trimmed delay line or something crazy like that, I guess.

We do make triggered oscillators, and this technique can test them too, for any selected edge after the trigger.

HP did make one timing instrument that started and stopped a crystal oscillator. It was awful. We make oscillators that start instantly but are phase-locked (or rather time locked) to a continuously running XO or OCXO. HP's 5359A and 5370 did something similar, locking a start-stop oscillator to an XO but preserving the timing of the async trigger.

Here's an instant-start oscillator:

That's sort of one of my hobbies, making instant-start PPB-accurate oscillators. The PLLs get mind-boggling.

Or do it in time domain.

Silly question, Why do you want to start (and stop) an oscillator? Is it to reduce the time uncertainty between the trigger pulse and the first clock edge?

George h.

Yes, to make XO-accurate low-jitter async-triggered delay and pulse generators.

Some of the techniques are mentioned here.

I wrote the "design" section.

"Ted Shot Dogs"? Ummm... I'm not really into eating dog, without or without the charcoal fire. Does the city really allow Ted to shoot wild dogs and serve them in his restaurant? Is Ted from Viet Nam?

I spent my first 50 odd years eating food like that. It was good, tasty, convenient and socially correct, but had its effects. I'm now spending the next 50 odd years doing damage control and trying to recover from the effects as best I can. I appreciate your good intentions, but such a meal would probably be considered a cholesterol, saturated fat, and salt overdose. I will confess to munching such items in small quantities, but a full dinner consisting of everything I've learned to avoid might be fatal.

When I travel to some place new, I try to find the local restaurants that specialize in salads. Google found this in Buffalo NY, which looks acceptable:

Just one problem. I have no immediate plans to travel to Buffalo. Thanks for the offer anyway.

Thanks, reading I thought of doing it the SRS way. (measure offset (skew) and compensate at the end.)

George H.

No problem, I tend to eat salads at lunch, (a belly full of grease sends me to sleep.) I think my waist line is mostly the result of too much beer.

I'm still waiting on a quote from Mike at Oscilent Corp. He does want to send me a sample before I order 100. (That's a good sign.)

So thanks again, I'll be eternally (well at least a week) grateful.

George H.

That works, but has a few minor problems. The input interpolation and output compensation have to match very well, or you get jitter. Insertion (minimum) delay and rep-rate are compromised by the input synchronizer and analog delays. And you need in effect a sample-and hold with fast acquisition and long (1000 second) hold, which gets to be a nuisance.

The Pepper patent was brilliant, but that DDG is no longer made. His actual circuit design was awful. It also had the analog sample-and-hold drift problem.

That is impressive. But how do you convert a rising edge to a single dot showing the probability? I particularly like the solid row of dots near the center, with no outliers. But it is not clear what you are measuring and how you get the results.

I have no idea what the Pepper patent is? I was thinking about this*, for short times do the SH thing and then for longer times A->D it. And subtract from the end.

(I've never 'done' (built my own) an A-D, only used someone else's.)

George H.

A high frequency pulse train was fed into the flop D input and another copy of the same pulse was fed into the clock. The edges were slowly swept across one another in time. The averaged (lowpass filtered) Q output at any time is the probability that the flop will get set to 1 by the pair of pulses.

The 50% probability point is the true setup/hold time boundary.

The non-integrated-gaussian appearance, the vertical lines, is probably the quantization of the DAC that did the time sweep. The curve was a lot steeper than we expected.

Here's the same experiment, but with different tempeartures.

It's referenced in the Wikipedia article. The patent is obscure, but basically he used a linear ramp to make delays, and paused the current source (by periods of a crystal oscillator) to get long delays.

Yes, in effect a compound analog + digital S/H. As I said, nuisance.

I did a few, in ancient times. SAR, dual-slope, V/F. No more.

Snicker. That's almost as funny as ExpertSexChange.com

Clifford Heath

OK, that makes sense. Thanks.

Why would the DAC quantization be different for the same data point?

Another possibility for the vertical lines is a small temperature drift during the measurement. Your temperature curves show a strong shift as the temperature changes.

Maybe it takes a small amount of time to measure and plot the data point, and a small temperature change could affect the result. Holding the delay at a constant value for these measurements could produce a different PWM value and give the vertical lines.

Maybe your noise floor is much better than you think!

The time shifts were actually small steps, controlled by a DAC, and the step size may explain the bands, if not the DAC resolution itself. I helped plan the experiment but I didn't write the code or run it.

The jitter equivalent noise floor of the flop is certainly a lot better than the graph suggests; the delay-sweep stuff is likely worse than the flop. We were hoping to get below 1 ps noise measurement floor, and it looks like we're at least 10x better than that. The flop costs something like $7, as compared to $50K of oscilloscope that we might have needed.

Jitter measurement with the flop is slow, especially for long delays, and temperature drift will be an issue. We need to find some temperature-stable coaxial test cables to connect to our DUT. Regular teflon dielectric cable has a horrible delay tempco.

I'm still not quite clear on how you're using this to measure jitter. Is there a block diagram anywhere? It's an interesting topic because high-speed ADCs work well at HF but aren't directly helpful for 1-pps edges that people also tend to want to measure. I'd like to be able to do both with one box.

Right now the state of the art for edge timing is a hybrid approach where ADC-based phase detection is used to measure ringdown cycles of a crystal or SAW resonator. Someone patented this scheme a few years ago, but not for the LC case if I remember correctly.

I haven't run into any obnoxious tempco effects with coax cables, probably because I never tend to use more than a few meters at a time and because there's usually a reference path that's just as long running right next to it. Crosstalk through single-braid RG58 is the big hazard around here.

-- john, KE5FX

Something like this:

Get a really good, maybe 10 MHz, OCXO.

Trigger the DUT (a digital delay generator in this case) from that clock, and also feed it into the flipflop D. The delayed output of the DDG feeds the flop clock. As we increase the delay of the DDG, we sample the square wave clock and see successive highs and lows at the Q output. Then we can play games, like slow-sweeping a transition to get a graph like I've posted, or just do go/nogo early/late tests around a transition (best for long delays if we don't want to test all day.)

This is to replace some old test sets that use HP5370s and Tek 11801s that are overdue for retirement. We can build a dozen tester boards and not worry about test fixturing for another decade.

To test other non-DDG gear, one would just insert a programmable delay in the test set, and still search for and play with the transitions. The delay could be a counter for coarse steps and a ramp for the fine stuff. Lots of possibilities, once we realize how good that flipflop is. The faster ADI comparators are at least as good, and have strobe inputs.

Teflon is horrible and polyethylene is pretty bad, delay vs temp. There are much better cables, a tad pricey.