SR Latch initialization on bread board.

I have been all over the place and cannot seem to find an actual explanatio n for one or many possible solutions on the race state of a SR Latch on ini tialization/power up

I have a small circuit on a bread board using an SR Latch, the circuit func tions correctly once power is on and the SR latch has been manually used to set the desired initial state.

But, the race condition when the circuit is powered is very indeterminate a nd it bounces back and forth to which state wins. But I cannot seem to find an explanation as to how to set the initial state properly and then have i t function as normal.

I have tried a few methods on my own but none seem reliable enough. Am I mi ssing something as it seems like it should be quite simple, but I have not seen a solution I can apply on my board. Either I'm blind and its right in front of my face or somehow I have been unable to Google it. Found a LOT of sites explaining the race condition, but no solutions on how to "set" it.

-E

Reply to
eric
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On a sunny day (Tue, 13 Aug 2013 22:08:50 -0700 (PDT)) it happened snipped-for-privacy@bauld.com wrote in :

Not sure what your problem is, but if you for example use a 74HC74 fliflop as set reset, you can keep the set (or reset) input active for some ms with an RC time so it always powers up in the required state.

As to 'oscillations' and 'race conditons'. I hope you no do use one of the flimsy solderless 'breadboards', a few ns bad contact and or slow edges will trigger a fliflop many times. So make sure you rise and fall times are within spec.

Reply to
Jan Panteltje

Flip flops come up in indeterminate states unless you do something explicit to reset them, or as Jan suggested, to make one input come up slower than the other.

Because a symmetrical flip-flop that happens to be half way between a 0 state and a 1 state is inherently indeterminate as to which direction its going to go, you're pretty much doomed to this problem unless you do something about it.

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Tim Wescott 
Wescott Design Services 
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Reply to
Tim Wescott

Use a good POR (power-on-reset) circuit that also copes with brown-outs. ...Jim Thompson

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| James E.Thompson                                 |    mens     | 
| Analog Innovations                               |     et      | 
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Reply to
Jim Thompson

Yup.

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Tim Wescott 
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Reply to
Tim Wescott

The problem is I don't know of any POR circuit examples handling a SR Latch. What I am trying to solve is the fact that on power up the state of the latch is indeterminate. I know what I want it to be but don't know how to ensure it starts in that state.

Or how would one make the input come up slower than the other? Bridge a capacitor on one side? I am doing this on a solder less bread board, but will be moving it to a protoboard once everything is figured out.

I have been doomed to the indeterminate problem but I don't have the knowledge or exp to know what solution is effective or "correct"

Reply to
eric

Virtually every chip I've designed in recent years has a complex POR. A recent chip monitors three separate supplies for value and sequencing before allowing the logic to fire up. ...Jim Thompson

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| James E.Thompson                                 |    mens     | 
| Analog Innovations                               |     et      | 
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Reply to
Jim Thompson

Im using

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For a chip and using two of the NOR gates to build a Latch
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I have 13.5v powering the chip. But I still don't follow how I can get this latch to power up in a specific state. Every time I restart it is seemingly random which side of the latch starts active.

Im not a EE, just a software guy trying that has really wanted to learn how to build electronics and is getting stuck.

Reply to
eric

Yes. That is typical, and is to be expected unless you do something special to make it not happen.

Getting unstuck will teach you a lot, though!

You've been given answers, but maybe not ones that are "unwound" enough to see them.

Since you're using NOR gates, I assume that your rest state has both inputs to the SR latch high. What you need to do is to make sure that on power-on, the correct input on each latch is held low long enough for the latch to assume your desired state.

One way to do that is what Jan recommended: you make sure that on power- up, one input always rises significantly slower than the other -- that input will force its corresponding output to be high when things have settled out.

Another way to do this is with an explicit reset circuit. You have a circuit that detects when the power supply is below some threshold, and as long as it is low, you hold selected inputs on your latches low. This is easier to understand at a glance of the schematic, and more reliable, but it takes more components.

I hope this makes sense -- if it doesn't, ask.

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Tim Wescott 
Wescott Design Services 
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Reply to
Tim Wescott

d

Thanks, I have learnt a lot already trying to figure this out. This is my f irst dip into IC's and circuit based logic. And really feel I have made pro gress, esp in understanding how little I know :)

I think my inexperience is culprit in not understanding the solutions prese nted. And I appreciate the help.

Now the power on state of the latch will have either R = 0 & S = 0 Or R=1 & S = 0, The problem is when when R = S = 0 and then the lat ch jumps into its race condition.

Not sure how a power on reset would work here, but I can understand putting a delay in between Q and S would yield the result I am looking for. And I would hope that it will initialize the latch with 'Q as high R=S=0.

Now, would a recommended method of doing this would be to put a capacitor o n the Q,S link and ground. Would this slow down the race condition enough t o allow the latch to initialize in the state I wish? Or is there another ex pected method used to cause this slow down?

For the explicit reset circuit, if one loses power. Regains power and once you are above the threshold and have proper power. How would the reset circ uit integrate with the inputs on the latches, would it just trigger transis tors on the RS inputs? Or would it have them in the way of the QS and 'QR p athways? Because if its simply Preventing the input on the RS side, won't I have the same race condition of the RS latch being R=S=0 and then one side "win ning" the race condition.

- E

Reply to
eric

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first dip into IC's and circuit based logic. And really feel I have made p rogress, esp in understanding how little I know :)

sented. And I appreciate the help.

atch jumps into its race condition.

ng a delay in between Q and S would yield the result I am looking for. And I would hope that it will initialize the latch with 'Q as high R=S=0.

on the Q,S link and ground. Would this slow down the race condition enough to allow the latch to initialize in the state I wish? Or is there another expected method used to cause this slow down?

e you are above the threshold and have proper power. How would the reset ci rcuit integrate with the inputs on the latches, would it just trigger trans istors on the RS inputs? Or would it have them in the way of the QS and 'QR pathways?

he same race condition of the RS latch being R=S=0 and then one side "w inning" the race condition.

And after typing up the reply I tried using a 1.8 uF ceramic capacitor on t he path between Q and the other input on the S NOR and ground.

And it starts up in the state I want/expect every time. I will have to twea k and see what value capacitor works best, as I think 1.8 uF is a little la rge but I don't have a background as to why that is just its physical size seems excessive.(Or I have a large capacitor, rated for 630v)

But still curious as to how the other methods would affect this circuitry.

Seems like it was such a simple solution (if correct) but something I was s imply unaware of.

- E

Reply to
eric

ion for one or many possible solutions on the race state of a SR Latch on i nitialization/power up

nctions correctly once power is on and the SR latch has been manually used to set the desired initial state.

and it bounces back and forth to which state wins. But I cannot seem to fi nd an explanation as to how to set the initial state properly and then have it function as normal.

missing something as it seems like it should be quite simple, but I have no t seen a solution I can apply on my board. Either I'm blind and its right i n front of my face or somehow I have been unable to Google it. Found a LOT of sites explaining the race condition, but no solutions on how to "set" it .

Assuming it has an Active Low reset pin, could you tie its Reset to ground through a large cap and series resistor, that way when you boot up the rese t pin will be held low until the cap charges up enough to decouple the rese t pin from ground?

Reply to
panfilero

ation for one or many possible solutions on the race state of a SR Latch on initialization/power up

functions correctly once power is on and the SR latch has been manually use d to set the desired initial state.

te and it bounces back and forth to which state wins. But I cannot seem to find an explanation as to how to set the initial state properly and then ha ve it function as normal.

I missing something as it seems like it should be quite simple, but I have not seen a solution I can apply on my board. Either I'm blind and its right in front of my face or somehow I have been unable to Google it. Found a LO T of sites explaining the race condition, but no solutions on how to "set" it.

d through a large cap and series resistor, that way when you boot up the re set pin will be held low until the cap charges up enough to decouple the re set pin from ground?

There is no reset pin I am aware of, the SR Latch is constructed from two N OR gates on a quad input NOR gate IC. If the latch was fully embedded into a IC instead of constructed from two N OR gates.. not sure I understand how the reset works in that case. Do you k now of a chip that has that functionality? Just so I can see it and try to figure out how that relates to what was previously brought up.

-E

Reply to
eric

On 8/

Study figure 2.

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What happens when you have this waveform on one input?

This is simple and will work for most power up conditions, BUT not all.

Reply to
amdx

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So far, no mention has been made as to how the latch's other input is 
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Reply to
John Fields

o NOR gates on a quad input NOR gate IC.

o NOR gates.. not sure I understand how the reset works in that case. Do yo u know of a chip that has that functionality? Just so I can see it and try to figure out how that relates to what was previously brought up.

Here is a pic of the circuit as it stands, I added the capacitor in and it has stopped the green LED from starting in a indeterminate state(Sometimes on sometimes off). That is only if the Trip Input is open of course. And the 100 uF cap on the power has been removed.

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- E

Reply to
eric

On a sunny day (Wed, 14 Aug 2013 15:15:19 -0700 (PDT)) it happened snipped-for-privacy@bauld.com wrote in :

-----------------------------------> to gate MOSFET 1 | | | 0 || | === ||-( reset | | 100n 0 || | /// | | /// | + | + | | | \ /LED | \ / LED --- | --- | | | 1k | 1k |------ | |---------------> to gate MOSFET 2 c | c | --b NPN -- b NPN | | e e | | | | | | /// /// | | | |-------------------------- | 0 || ||--( set 0 || | ///

2 transistors

In fact IIRC you do not need any semiconductors at all, can be done with relays.

I once made a MVB with one relay and a capacitor for flashing sign (for some fun thing) .... Had to bend the contacts a bit... would not last that long. Maybe it had a resistor too...

Try it with 2 relays only, the set-reset.

There are those pulse relays... those stay in one position, now you only need ONE relay. Weight is important on your trip to space.... :-)

Reply to
Jan Panteltje

Thanks, but not sure I quite follow. Trying to relate your design with the overall design on the logic diagram.

Intention is that:

1) On power up neither relay is on 2) On momentary reset relay /w green is activated 3) If at any time trip is closed, green side is off, red is on 4) If reset is hit while trip is still open, nothing happens 5) if trip is open then reset will function and be able to trigger green led 6) At no time will both red and green be active 7) On init neither LED circuit is on

The overall circuit is not a SR Latch, it has a few required tweaks to follow the above rules.

Or were you just replacing one of the SR latches ?

Reply to
eric

On a sunny day (Wed, 14 Aug 2013 23:20:29 -0700 (PDT)) it happened snipped-for-privacy@bauld.com wrote in :

Yes those are diffrent specs than the original SR latch you mentioned.

If it gets complicatiatered use a PIC. :-)

It can drive the LEDs too, logic level MOSFETs, and has many more inputs for 'buttons'. And remote conrol.. RS232

2$, internal oscillator, brownout, safe power up, etc etc, watchdog...., micro amp current.... Beat it!

Your description, logicaly speaking, is not very clear.

Reply to
Jan Panteltje

anation for one or many possible solutions on the race state of a SR Latch on initialization/power up

t functions correctly once power is on and the SR latch has been manually u sed to set the desired initial state.

nate and it bounces back and forth to which state wins. But I cannot seem t o find an explanation as to how to set the initial state properly and then have it function as normal.

m I missing something as it seems like it should be quite simple, but I hav e not seen a solution I can apply on my board. Either I'm blind and its rig ht in front of my face or somehow I have been unable to Google it. Found a LOT of sites explaining the race condition, but no solutions on how to "set " it.

und through a large cap and series resistor, that way when you boot up the reset pin will be held low until the cap charges up enough to decouple the reset pin from ground?

NOR gates on a quad input NOR gate IC.

NOR gates.. not sure I understand how the reset works in that case. Do you know of a chip that has that functionality? Just so I can see it and try t o figure out how that relates to what was previously brought up.

The SR latch has 2 inputs S = Set and R = Reset. You can make it out o f two NOR gates or two NAND gates, if you make it out of NOR gates then you must hold your reset pin high until your chip boots up, if you make it out of NAND gates you hold your reset low until your chip boots up. Holding t he reset pin in this way until your chip powers up could help you always b oot up into the same state.

Reply to
panfilero

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