Spacing between high voltage and low voltage traces and layers.

I know that UL requires 3/32" (1/8" to be safe) between high voltage traces and 5V digital traces.

That's only "air" separation, right? What about multilayer (4 layers to be exact) boards, can I have the high voltage/high current traces run above and/or below the 5v digital traces, since there is some insulation in-between the layers - and not violate UL's minimum separation rule?

Thanks, Mike

Reply to
Mike V.
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Reply to
Xrayjuan

What are you considering "high" voltage? The old rule of thumb was for FR4 at least 1" per 10KVDC with NO sharp component bends and no right angle traces (cause of the sharp edge). You could get closer with a good conformal coating or potting. I don't know what the UL requirement is. They tend to get nervous at anything over 42 volts.

Tom Woodrow

Mike V. wrote:

Reply to
Tom Woodrow

Hi Mike,

I consider high voltage traces bridging across low voltage areas dangerous no matter what. You would be relying on the properties of a material that is probably not controlled in house but by a third party. Even if they guaranteed a certain breakdown voltage, if something goes wrong your company or worst case you may be on the hook.

Once I saw what happened when somebody cut it too close. Not a single chips survived and some looked like Mount St.Helens after it blew. Luckily nobody was hurt.

Regards, Joerg

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Reply to
Joerg

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