source for 55Mhz crystal/oscillator

I don't see why not - but I can't seem to find a suitable stocked part. Can you suggest a part number?

Not sure how you define "expensive", but Digi-Key will program and sell you several different kinds of programmable oscillators. They offer parts by Citizen, ECS, Cardinal, and Epson that run from $5 to $11 in quantity 1. They also have Epson 55 MHz crystals in a couple of different packages - SE2552CT-ND or SE3456-ND - for about $1 each. They even have a 55 MHz Epson oscillator SE2855CT-ND for $6 each.

Matt Roberds

I'm designing a board for that very chip right now, I think you may be making a mistake. Read the datasheet carefully -- the chip expects a

3MHz to 20MHz crystal or a clock source of up to 50MHz. (See the Electrical Characteristics section.) Of course, this is a preliminary datasheet and these specs may be in error. (I would suspect there's a good chance that the 50MHz spec is an error, and ought to be 55MHz, but you never know.)

But as far as I can tell, you're expected to use the on-chip PLL if you want to run at the maximum core frequency of 55MHz. Note also that if you want to use USB, you have to generate 48MHz, 96MHz, or

192MHz +/- 0.25% from the PLL, and if you want to use USB with the on-chip bootloader (SAM-BA), you need an 18.432 MHz crystal, from which the PLL can generate exactly 48MHz, and from which you can generate very close to 55MHz once you've got your own code in control of the PLL if you don't need USB.

My understanding of all this could be wrong -- the datasheet is very unclear on certain things.

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Randall

I think you're absolutely correct. I had been wondering why on the dev board they used an 18.432Mhz crystal. So am I understanding your post correctly in that the master clock has to be 48Mhz for USB to be functional? Would it be possible to normally run at 55Mhz and then when a connection is detected on the USB connector have it switch down to

48? Thanks,

-Michael

Would a Fox module do?

Ken

On 2005-09-13, Michael J. Noone wrote: [...]

Caveat lector -- I'm basing all my answers on my reading of the preliminary datasheet. I haven't managed to get my hands on a part yet, so everything I say could be wrong.

The short answer is yes, I think so.

This chip has lots of clocks, and it took me some time to sort it all out, so I might as well share what I learned. The fundamental clock sources are the internal RC oscillator (SLCK or "slow clock", nominally 32.768kHz, but not very precise or stable), and the main clock, driven by either a crystal oscillator or an external clock source. Note that this is called the "main" clock (MAINCK), which is different from the "master" clock, but before we get to that there's also the PLL clock (PLLCK), which is driven by the main clock and includes a programmable divider and multiplier. This results in three primary clocks available in the system - slow clock, main clock, and PLL clock.

The master clock (MCK), which you mention, can be based on any one of these three clocks, and further more it has a power-of-2 prescaler which can divide the clock so that the MCK is slower than its source if you like. The MCK is the source for the processor clock (PCK) and all the peripheral clocks, except for the real time timer (which, regrettably, must use the slow clock, and therefore can't be relied upon for long-term stability), the other timer/counters (which have many possible clock sources, but that's irrelevant to our current discussion), and, finally getting to your question, the USB clock (USBCK). The USB clock can be driven only be the PLL clock, though there is a divider which can divide PLLCK by 1, 2, or 4. So, if you want to use USB, PLLCK must be 48MHz, 96MHz, or 196MHz, +/-0.25%.

So what's the net effect of this, if you want to use USB? USBCK must be driven by PLLCK, which must be driven by MAINCK, which can be driven by either crystal oscillator or external clock source. MAINCK, therefore, must be chosen such that the divider/multiplier in the PLL can scale it to a precise multiple of 48MHz, and 18.432MHz happens to be a good choice for this (*125 /48). This, unfortunately, limits your master clock, which drives the processor, to either the slow clock (probably not what you want), or something based on 18.432MHz. You can get very close to 55MHz from 18.432MHz by using the PLL (*185 /62, for example), but you can't use the PLL for this at the same time you're using it to drive USBCK at 48MHz. So, while you're using USB, you have to run the master clock at either 48MHz, 18.432MHz (straight from MAINCK), or 32.768kHz (SLCK).

But, you absolutely can reprogram all the clock sources on the fly, so long as you follow the procedures documented in the datasheet, so that you normally run at close to 55MHz but reprogram the PLL and drop down to 48MHz when you need USB. Note that you'll have to have the USB peripheral completely disabled while at 55MHz, so you'll need another way to detect USB (sensing voltage on the USB +5V pin, for example).

Hope that helps, and please correct me if you find that I'm wrong about any of this!

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Randall