I'm starting to layout a circuit. The board is ~3" x 6" and on one of the skinny edges, inputs for power and signal in/out. (DB9 and DB15) The whole circuit mostly wants to live close to this edge... all crowded. So I was thinking about running traces from the power inputs around one edge to the far side of the pcb. Then power comes in on one side and signal in/ out the other... and the signal flow is easier (at least for me) to think about.
Run them (pwr+GND) along the edge on opposite sides. his way they are not in the way for other traces and cancel out their magnetic and electric fields.
Well, easy solution to half of that, tie ground to plane so it routes everywhere by default.
Any filtering necessary for the power, still has to go by the connectors. That way you get the benefit of star grounding, to some extent or other.
I'm guessing the circuit isn't bleeding fast, so it won't mind being expanded to fill the board area, no need to crowd the connectors. :-)
Some words on routing:
If four layers, no problem, route away. Use outer layers, and GND/VCC inner layers. (Use vias liberally, to get short GND return paths.)
If two layers, consider the board as GND plane on one layer, and components and routing on the other. (VCCs must be routed as ordinary signal traces.) You will inevitably need to cross traces, so drop vias to the bottom side to do this with as little disturbance (bottom-side trace length) as possible.
Then, fill the top side with ground too, and stitch all the islands and peninsulas (and periodically beside long traces, say every inch or so) with GND vias.
Actually, it may be worthwhile to make a slight exception to the first rule (minimum disturbance), to allow top side ground to flow around vias at trace crossings. Takes up still more space, but often an option to save a stitching via or two.
If the layout is too dense to allow this kind of layout (fully routed on the top side plus crossings), then the next best level of density is to use layer bias. Route nearby connections straight in where possible, but otherwise, prefer a bias to the top side, say vertical, and the opposite (say horizontal) to the bottom side. Expect to use more vias. (It's fine, vias are free.)
Keep in mind that component pads act as rows of barriers, semipermeable if widely spaced (SOIC, DIP) but otherwise impassable (TSSOP, etc.), and what's worse, needing connections themselves. Try to reserve enough space between ICs (and rows of resistors/capacitors) to allow these routes to resolve.
Main routes between subcircuits, prefer to bunch traces into buses and route them vertically and horizontally for each layer.
What's really most important is making crossings in the same way as before: bunches of traces on top and bottom, crossing with minimal disturbance to ground pour. (Note that, anywhere two traces cross, there is a hole completely through the top and bottom ground. Two buses crossing makes an even bigger hole.)
A strict directional bias isn't necessary; the directions can swirl around like magnetic field lines, with perpendicular electric field lines on the other layer. But everywhere you change direction, you need to remember it, and keeping track of this across a board can get onerous.
So, in case it isn't clear -- try to avoid routing under components, because, then you'd have to stitch under the component too, and things quickly get messy. (But again, rows of pads are connections, and that's often necessary. Try to keep ground filling as much as possible.)
The ultimate result of 2/3 is to have effectively a one-plane construction. It doesn't really matter where components are placed or traces/buses are routed, so long as there's always ground on the opposite layer, with as few exceptions as possible (crossings). With this done, you get a layout from 2 layers that's as good as (potentially even slightly better than) a 4-layer (inner planes) design.
This is applicable to high speed and RF* circuits, switching supplies, low EMI emissions, and excellent EMC susceptibility.
*Given that the trace impedances are fairly high, ~100 ohms CPWG (coplanar waveguide with ground -- that is, a trace routed through a pour on the same layer, with ground pour on the opposite layer), for typical trace and space. This may require some changes to the datasheet/appnote case, and may affect bandwidth (e.g., you could route and terminate LVDS traces at 200 ohms differential, but you suffer more attenuation over long routes, and slower risetimes due to pin capacitances). RF works just fine, given the same limitations obviously, with it just being a bit harder to find filters, transformers, etc. that start with a 100 ohm system impedance.
I've done boards where the back side was a "comb" of power and ground fingers reaching in from opposite edges, and the top was mostly signal. It wasn't a particularly fast board, but I did decouple the power/ground pours at many places, so you get 0.1uF at each chip, 1uF sprinkled around to decouple the two pours, and 10uF at board entry.
I think the key thing to remember is that if you have "fast" signals (sharp edges) you need to consider where the return path is, and add decoupling where that path changes pours.
Of course, 4 layer PCBs are cheap enough these days that you might consider going that route :-)
Most boards can be laid out and power copper can be poured around the trace s. This creates a capacitor with the ground plane. The capacitance may no t be large, but the quality factor is huge and the inductance low providing decoupling well into the GHz range. I'm pretty sure you don't get any of that with interdigitated power and ground.
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Rick C.
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Hey, thanks all... I just needed a different way to think of the layout. Iv'e now got the two signal chains running in and along the edges, and a reference voltage chain coming from the back and down the middle, that makes the PS rails nice. (mostly dual opamps)
So here's a real question; At the end of the thermal chain I've got a TCA3072 feeding a ~100 ohm (100 to 300 at the moment) heater. from a 24V supply. TCA here (only available in case 751G AFAICT)
That case style has four leads to the negative rail, I assume that is a thermal connection, and soldering those to a big piece of copper pcb is what I want heat-wise. Is that right?
Tim, one thing I wanted to add to that nice list; When I have to overlap, power supply traces are my first choice, 'cause they are next closest to gnd.
Yup, effectively the power supply traces are a narrow pour, stitched with frequent bypass caps.
Linear routed supply is also easy to do PDN analysis on. You need more caps (potentially one or two per IC, as conventional rule of thumb suggests) than in a 4-layer build, but it's also a well known impedance, which is nice.
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