Signal Integraty Schematic

I am new to board design and trying to learn Signal Integrity Analysis. Please find the link below for the schematic as shown in Fig

3.1 where as Fig 3.2 and Fig 3.3 are equivalent Signal Integrity Schematics.

formatting link

All three figures are from the first example in the HyperLynx manual. Can anybody explain how does the Fig 3.1 translate into equivalent SI Schematic as shown in 3.2 and 3.3? i.e which net in Fig 1. translate into which transmission line in Fig 3.2 and Fig 3.3?

Thanks in Advance Mahen

Reply to
Mahen K
Loading thread data ...
O

Hum, there is a lot of missing data, board layout, board material, gate delays, chip package, trace widths, chip pin input model etc...

You can't do that direct from the circuit, you need the physical model.

You need to model how sharp pulse edges, which correspond to RF, propogate in space on a small scale,

The SI schematic depicts RF transmission lines.

I suggest you find a mentor or teacher who knows what they are doing, this is a long project and much of it must be learned intuitively.

I also suggest you download HP APPCAD

formatting link

and OCTAVE for linux.

formatting link

then

formatting link

And see if the library has a copy of

formatting link

Google, shorted, half wave, quarter wave, and open transmission lines, then S parameter, Smith Chart, and RF termination. VSWR is in there too, but much of what is written on line on that topic is false.

Good Luck, Find a good instructor! Then come back here to ask specific questions.

Steve

Reply to
osr

snipped-for-privacy@uakron.edu Inscribed thus:

I agree with Steve there is lots of data missing that is needed. However I'll have a go at explaining what I think it getting at. One is impedance matching. Basically transforming the impedance seen at one end of a transmission line to match that at the other. This is done by controlling the transmission line characteristic impedance. Second is to delay a signal by a specific amount amount so that it arrives at the right point in time. This is done by controlling the transmission line length.

As Steve implies this is not a simple exercise but requires fairly complex math, hence the "Smith Chart" recommendation.

--
Best Regards:
                Baron.
Reply to
baron

Thanks a lot for the pointers for further reading. The example I quoted was from Mentor's Line Sim (Pre Layout) simulation manual. So board ayout, material etc are not yet considered. Am I missing something here/

-Mahen

Reply to
Mahen K

ElectronDepot website is not affiliated with any of the manufacturers or service providers discussed here. All logos and trade names are the property of their respective owners.