Shift register power on.

I'm using one of these - a serial/parallel shift register.

It's straight forward enough except when it comes to startup. The master reset only affects the internal shift register, not the stored outputs, so if OE is low at power on, random outputs will appear. To avoid that I seem to have to hold OE high while MR is held low to clear the shift register, then have a rapid transition on the storage register clock input, and only then bring OE low to enable the outputs.

In practice, I'll not bother with MR, and instead just clock enough zeroes in to clear the shift register.

That still leaves me with having to control OE for the sole purpose of preventing random outputs during initialisation. Were it not for this, I'd just tie OE low, since I don't need the tri-state output function.

I'll have to dedicate a scarce microcontroller pin to this, and propagate it across several boards.

Surely it shouldn't be this complicated.

Sylvia.

Reply to
Sylvia Else
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That's pretty bad. MR should clear everything. And OE floats the outputs, which may make trouble for you.

We use a lot of TPIC6595s as relay drivers, and it has the same silly architecture. We disable the outputs (with the /G pin) until after the first full shift/latch cycle. But then we don't need to use SRCLR, the half-ass reset.

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This works. The tricky part was distributing the serial clock to 34 big relay driver chips wired as one giant shift register.

You could save one port pin and one wire by holding OE false after powerup, until the strobe. That would need a little local circuit on each board.

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John Larkin         Highland Technology, Inc 

lunatic fringe electronics
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Reply to
John Larkin

Fortunately, it won't matter in my particular application.

It's difficult to fathom the motivation. It lets one clock in data faster when it has high order zeros, but who would even bother? Perhaps there's another way it could be useful, but I can't see it.

Sylvia.

Reply to
Sylvia Else

use something like a 'HC74 d-flop. /clr to your board/uC /por. /pre and /oe to /q and /mr to q high on the D input. clock it and stcp once. You might need to pull up /pre to make sure it's stable. You may need to use the other half of the '74 to give you a 1 clock latency on the stcp and /mr transition.

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Chisolm 
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Reply to
Joe Chisolm

MSI was never intended to be a one chip solution to many problems. Why not use a more suitable part? There are any number of I2C and SPI driver chips that are much better parts than an 8 bit '595.

MC33996, TLC5922, MAX6966 and many others.

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Rick C
Reply to
rickman

Pull-up (or pull-downs) on the Tristate outputs.

Cheers

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Martin Riddle

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Reply to
bloggs.fredbloggs.fred

If I understand your description correctly, then a 74HC164 is much better suited for the job than the HC595. The HC595 only does you anything good, when you have to catch a byte transition on the parallel input *while* you are transmitting, i.e. shifting the SR.

Klaus

Reply to
Klaus Bahner

The '164 shows the contents of the shift register as they change, which wouldn't be good if (for instance) you wanted to hold Q0 at 0 while toggling Q3.

The '595 holds the output constant until you tell it, at which time it switches.

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Tim Wescott 
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Tim Wescott

Shouldn't be.

Small, low-power CPLD? Yes, the task is vast overkill for such a beast, but it'll work.

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Tim Wescott 
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Reply to
Tim Wescott

If this is an issue, then the HC594 as suggested by Fred before seems to be the solution to Sylvia's problem.

Reply to
Klaus Bahner

+1 -- assuming input low current is essentially nonexistent.

I've used a SIP resistor array driven from an output to "force" multiple pins high and low, programmatically (e.g., to detect if the signals that *should* be sourced on those pins are, in fact, present as well as force them to specific states when "disabled")

Reply to
Don Y

That's the part she's having problems with, and if you look at the data sheet it certainly indicates that the reset only goes to the shift register and not the shift-capture register.

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Tim Wescott 
Wescott Design Services 
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Reply to
Tim Wescott

Maybe not; can you put in a latch, set HIGH by MR, and only set LOW to enable the outputs by the first or second STCP , with the latch output driving \OE? Or even a retriggerable one-shot, to make a 'slave reset' signal that lasts a short time after the master reset (yeah, I know, it's ugly to include timed logic).

There's probably lots of uses for multiple non-master resets, but i doubt you'd want to commit to an I2C addressable latch for just one little 'not-yet' signal.

Reply to
whit3rd

Not really. She is using the 595 which has tristate output control which she doesn't want and the 594 has an output register reset which could be connected to the same pin as the shift register reset which would do exactly what she wants.

I can't remember the last time I used a 7400 type device other than a bus buffer and that was actually a level shifter chip.

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Rick C
Reply to
rickman

Whoops -- missed that. I just read up to the HC59 and phased out. Thanks.

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Tim Wescott 
Wescott Design Services 
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Tim Wescott

Actually, an I2C latch reduces my component count considerably. Some of the outputs from my 5 cascaded shift registers were to drive a diode matrix to let me sample multiple inputs. I can substitute 3 I2C latches, and read the inputs directly.

Sylvia.

Reply to
Sylvia Else

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