Serial interface and logic analyzer

Hello,

I have following signals coming out of the CPLD

  1. Tag
  2. Data
  3. SCLK ( 3MHz)
  4. DCLK ( 1.5MHz)

Please go to the following link to look at the timing relationship of the above mentioned signals

formatting link

I am trying to look at these signals using logic analyzer ( HP

1661ES). The logic analyzer offers three different analyzing modes to look at the signals

  1. timing mode

  1. state mode
  2. State and timing ( both together, timing analyzer gets trigger by state analyzer)

I want to trigger the logic analyzer in the right way to see the right results. Can somebody advice me which mode to choose?

Thanks John

Reply to
john
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If HP uses the same terminology as my Dolch, then state mode. TAG low as a qualifier plus rising edge of DCLK -> Sample the data line. If you have to organize the data in a more fancy fashion you'd have to set it up more nifty so it first looks for a TAG falling edge, then keeps looking for DCLK rising edges and samples the data, then stops sampling once TAG rises and writes the next set into another line so it's easier to read.

One word of caution here. I've had situations with SPI buses where a device for some reason wanted to read data on the rising edge even though the datasheet said falling edge or vice versa. One was an ADC. So I called and after some hmms, ohs and ahems the app engineer said "Well, then just use the slope that works".

--
Regards, Joerg

http://www.analogconsultants.com/
Reply to
Joerg

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