Hello,
I have following signals coming out of the CPLD
- Tag
- Data
- SCLK ( 3MHz)
- DCLK ( 1.5MHz)
Please go to the following link to look at the timing relationship of the above mentioned signals
I am trying to look at these signals using logic analyzer ( HP
1661ES). The logic analyzer offers three different analyzing modes to look at the signals
- timing mode
- state mode
- State and timing ( both together, timing analyzer gets trigger by state analyzer)
I want to trigger the logic analyzer in the right way to see the right results. Can somebody advice me which mode to choose?
Thanks John