Interesting:
| Delay (us) | Jitter (ns pk) | 5.7 | 460 | 2.92 | 170 | 1.45 | 26 | 0.72 | < 10
Input is a linear capacitor charging slope. Delay is the time taken from the reset voltage (about 0.5V) until crossing the input threshold. Schmitt trigger is 74HC7014, a very handy little chip.
Actually, it's not little, they don't make a TSSOP. But SOIC is good enough.
Anyway, the jitter seems to go up much faster than proportional. Or, that it has a threshold.
Tim
-- Seven Transistor Labs, LLC Electrical Engineering Consultation and Contract Design Website: http://seventransistorlabs.com
You're not giving us a schematic. I suspect that some of the source of jitter is more or less noise on the input side, which will cause jitter that is more or less proportional to the delay. I suspect that the rest of the jitter is more or less internal to the part, which will be more or less constant.
All of the "more or less" waffling is because I've never tried to use one of these things where precision really matters.
-- Tim Wescott Wescott Design Services http://www.wescottdesign.com I'm looking for work -- see my website!
The 74HC014 creates hysteresis by switching in series and parallel devices to change thresholds. A "soft" transition slowly moves the threshold, thus the jitter. ...Jim Thompson
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| James E.Thompson | mens |
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Schmitt gates are not precise, and threshold varies with temperature and Vcc. A tiny amount of induced 60 Hz or EMI will add jitter, especially if you have a small timing capacitor. Do your longer delays use smaller caps?
Our ROT for RC-ramp (or current-source-C) delay generators is that RMS jitter is roughly 1/20000 of delay, using a real comparator.
A clean fast edge run through a cmos or even ttl gate might have a few ps RMS jitter.
-- John Larkin Highland Technology, Inc picosecond timing precision measurement jlarkin att highlandtechnology dott com http://www.highlandtechnology.com
The schematic is as simple as I can describe -- a diode discharges a capacitor, then lets it charge (from a PNP CCS). Cap voltage goes to Schmitt trigger and that's that. So it delays the rising edge by I = C * dV/dt.
The strange thing is it's not zero at zero. Plot the points -- the intercept is at 1.22us (delay), with a slope of 102 ns jitter per us of delay.
I suppose I'd expect the "zero" to floor at the device's intrinsic jitter (which is probably
"Jim Thompson" wrote in message news: snipped-for-privacy@4ax.com...
Sure, but why does that make it more prone to jitter? Because it's putting the input stage in the class A range, with very damn near zero offset (between input level and threshold, because the threshold is a sliding target), so the loop gain is very high, greatly amplifying internal noise?
Then, could a very poor gate (poorly designed, or poorly constructed), and a sufficiently slow input transition, actually cause output bounce because the internal state is amplifying that noise?
Tim
-- Seven Transistor Labs, LLC Electrical Engineering Consultation and Contract Design Website: http://seventransistorlabs.com
I was very particular to say 74HC7014, not 74HC14. Look it up!
Good question. I didn't mention what was varying in the test.
Same cap, different current. It's a 47pF cap, FWIW.
The '7014 is peculiar, so it's not clear to me whether it has a comparator structure or a more conventional CMOS Schmitt trigger structure (just cleaned up or compensated somehow to achieve the relatively precision threshold). It's definitely not a "real comparator", in the sense of one with 1000s of voltage gain, and GBW to spare, where you'll get a nice sharp ratio like that.
I would expect jitter as a ratio of delay, but the offset is weird.
Tim
-- Seven Transistor Labs, LLC Electrical Engineering Consultation and Contract Design Website: http://seventransistorlabs.com
At 'slow' slew rates on input, the Schmitt threshold is met when the transistors are only half-conducting. There's positive feedback, which is why the rise time on output is so good, but even positive feedback has some delay (internally), so it might be as simple as resistor noise in the near-threshold transistors.
The output pins are buffered, so this high impedance isn't something you can probe. It might be possible, though, to quantify the jitter for a long sequence of transitions, and look for it to have Fourier components (from power supply) or be spectrally white (as resistor noise would suggest).
I have some device-level schematics, so, with a free moment I'll simulate it. My reflex response was based on the rounded "knee" that results during such a slow transition. ...Jim Thompson
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| James E.Thompson | mens |
| Analog Innovations | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| STV, Queen Creek, AZ 85142 Skype: skypeanalog | |
| Voice:(480)460-2350 Fax: Available upon request | Brass Rat |
| E-mail Icon at http://www.analog-innovations.com | 1962 |
I'm looking for work... see my website.
Your writing is so terse I can barely understand what you are saying. "it's not zero at zero" means what? What is the first zero (or not zero) and what is the second? What are your X and Y?
-- Rick C
"Jim Thompson" wrote in message news: snipped-for-privacy@4ax.com...
Oh, cool, thanks.
Would it help to measure supply current versus input voltage? That would show the class A range (if not just the input stage current).
Having made a functional model of this part myself, and having purchased actual parts, I suppose I should verify it, too.
Tim
-- Seven Transistor Labs, LLC Electrical Engineering Consultation and Contract Design Website: http://seventransistorlabs.com
Considering how lengthy I write, most times, I guess that's a compliment!
Unpack that as "[the jitter] is not zero at zero [delay]". The zero intercept occurs at nonzero delay.
Just... look, don't gloss over the numbers, actually plot them on a graph! I wrote them down for a reason! :)
Tim
-- Seven Transistor Labs, LLC Electrical Engineering Consultation and Contract Design Website: http://seventransistorlabs.com
Go for it. One other thought... a slow transition is holding the devices in a regenerative region for a significant amount of time... regenerative receiver of noise... or making its own noise with a bump in supply current? ...Jim Thompson
--
| James E.Thompson | mens |
| Analog Innovations | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| STV, Queen Creek, AZ 85142 Skype: skypeanalog | |
| Voice:(480)460-2350 Fax: Available upon request | Brass Rat |
| E-mail Icon at http://www.analog-innovations.com | 1962 |
I'm looking for work... see my website.
Not zero, zero means there's some offset. (says the man, who mistook j*omega*tau, for an RC decay. :^) George H.
I actually looked at the data in the reverse direction; I wondered why the jitter shrank so fast with shorter durations.
If it's noise, the noise distribution will matter. If there's little high frequency noise, more low frequency, you'll get less jitter with short durations than with long.
5.7us seems a little short to be flicker noise though, unless as others have pointed out, there's a lot of gain around the threshold.Clifford Heath.
How exactly do you get zero delay in a circuit that charges a capacitor? Regardless, I don't know why you would expect *zero* jitter regardless. First, your rising edge is never zero time which is what should be the abscissa, the rise time, not the delay. They are related, but not identical. Second, there are always other sources of jitter in your measurement. You still haven't told us the details sufficiently to figure out where jitter might be entering the circuit.
So show us the graph! I don't get your earlier comment about the "intercept" being 1.22 us of delay. If delay is the abscissa, the intercept is usually considered to be the point where the curve crosses the ordinate. So the intercept should be given in ns, well less than 10 ns. Unless you are trying to say the Y intercept is negative and the jitter plot is zero at 1.22 us delay?
-- Rick C
I'm not clear on what you are saying. The 5.7 us is just the delay which is not important. What is important is the slope. The slower slope to get the 5.7 us delay provides a longer time for low level noise to affect the threshold crossing. The frequency of the noise won't affect the measurement unless the noise is correlated with the edge.
-- Rick C
Ok, I plotted the data... which was a bit of a bother because you inserted those separators. If it had just been numbers I could have copied and pasted the whole list at once.
So the linear equation is jitter = 94.06 * delay (us) - 87.22 ns and the Y intercept is -87.22 ns while the X intercept is around 0.9 us.
That is a bit goofy. The actual curve appears to roll off to an asymptote as the delay approaches zero. I can't think of a physical reason for that to happen.
-- Rick C
TTL/CMOS power lines are always horribly noisy, and there's not a lot of power rail rejection in things like the 74HC7014.
ECL - as current steering logic - has much quieter rails.
-- Bill Sloman, Sydney
OK, that probably has more jitter than an HC14. It's very slow.
Is the setup shielded? I like Danish Butter Cookie cans.
-- John Larkin Highland Technology, Inc lunatic fringe electronics
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