Running out of ideas: stability, bootstrap

Hi, all,

we had a bank holiday here, nicely positioned close to the weekend and I took the free time to play with my multi-IF3601 low noise amplifier.

That was not so funny because it features a negative input impedance over most frequencies, so with a suitable inductance on the input it makes a stable oscillator.

Some observations:

- Zin is negative also with the feedback loop cut

- Choice op op amp does not matter: ADA4898 vs. THS4022

- There is no coupling via the bias system; base bias used to have a 2nd current source that shared the BAV99 string; that could produce startup problems (solved)

- type of cascode transistor did not make much of a difference, using an Infineon BFQ19S instead of FZT851/ZXT690B looked slightly better, but not good enough.

- Leaving the cascode transistor out remedied the situation, but I need the cascode transistor to introduce the bootstrap to eliminate Cgd of the paralleled FETs.

- The THS4022 suppresses the Miller effect quite nicely at least to 100 KHz, but the unmultiplied Cgate-drain is still easily a nF of more.

- The obvious solution of gate stoppers does not make sense because of the noise. A resistor in the base lead of the cascode makes things worse; 6R8 between the drains and the cascode emitter made no difference. (could not use more without messing up the DC operating point, it also would interfere with the bootstrap)

- ferrite beads in the gates do exactly nothing.

circuit snippet is at <

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Currently, there are 4 FETs in parallel.

Does the combined expertise of the group have any idea on how to stabilize the cascode or an alternative way to introduce the bootstrap?

Best regards,

Gerhard

Reply to
Gerhard Hoffmann
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Did you check out some of the ideas guys had on the thread "Fast buffer idea?"

As JL might say, this cascode bootstrapping arrangement looks way too complicated and uses too many parts. I don't completely understand it. Why not drive the boostrapping transistor from its base?

:-( the mindset is catchy apparently...

Reply to
bitrex

Over what frequency range is the Zin negative?

Where does GATE_BIAS come from?

How is this physically assembled?

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John Larkin         Highland Technology, Inc 

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Reply to
John Larkin

Am 28.05.2017 um 18:46 schrieb John Larkin:

The network analyzer starts officially at 300 KHz, non-guaranteed at 150KHz. At 150 KHz Zin is already negative. It seems, at about 10 MHz everything is running out of steam, so it stops being offensive.

Every impedance inside the circle that goes through 0 has a positive real part. Everything on the circle through 0 has zero Ohms, only LC. Everything outside of that circle has a negative real part. The Smith diagram is in the same photo album.

There are no complaints by LTspice. In a very old version of Genesys, I get about the same behavior regarding Zin. But I could not make the bias loop converge, so setting the operating point is clumsy.

That comes from an integrator. I have added that part of the circuit. Since the 30uF input capacitance

  • 66Meg bias resistor takes an eternity to settle, I have added a window comparator & analog switch to reduce the bias resistor by paralleling 4Meg7. That works.

It is all on a small dual-sided circuit board. Pic included. It does no longer look that tidy. :-)

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and the pics left/right of it.

cheers,

Gerhard

Reply to
Gerhard Hoffmann

Am 28.05.2017 um 18:09 schrieb bitrex:

The bootstrapping is not yet included in the board; only the cascode as a precondition. The cascode also gave quite a rise in bandwidth when I used the ADA4898 and better Miller killing abilities at up to 160 mA.

I first wanted to drive the base from a leftover FET opamp used as a follower; OTOH the same voltage is available at the sources of the IF3601; a 0.1 Ohm source resistor looks impressively low impedance, but at this point the signal has already travelled through the cascode and the THS4022 op amp, that introduces unwelcome dependencies.

The 0.1 Ohms look small and everything seems common source, but the feedback through the op amp makes it behave like a high impedance current source from the FET's point of view. The source follows the gate quite closely after all.

The drain looks into ~ 0 Ohms of the cascode emitter, and if the signal fed back from the op amp has the right phase, it looks capacitively for the FET. That alone could provide the negative input impedance (like in a standard VHF VCO, aka capacitivly loaded follower).

Only the fact that Zin is still negative when I cut the feedback makes me assume that the cascode transistor is the culprit.

The 0.1 Ohm source resistors btw were necessary with 8 parallel FETs, or they would cost 10 pV/rtHz in simulation when you are just at +/- 100 pV/rtHz.

Cheers, Gerhard

(got a nice Tempranillo)

Reply to
Gerhard Hoffmann

Though it says C4, dni, is it there? Maybe the capacitance at that node is making Q3 unstable? ...Jim Thompson

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| James E.Thompson                                 |    mens     | 
| Analog Innovations                               |     et      | 
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Reply to
Jim Thompson

Am 28.05.2017 um 23:30 schrieb Jim Thompson:

No, it is not there, just an opportunity so solder something.

But adding a capacitor of 150p between base and C of the cascode improves the situation slightly, although not enough, and it looks wrong.

cheers, Gerhard

(getting tired slowly because of said Tempranillo :.)

Reply to
Gerhard Hoffmann

Strange.

Enjoy >:-} ...Jim Thompson

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| James E.Thompson                                 |    mens     | 
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Reply to
Jim Thompson

Which feedback loop? There are two that I see in the circuit as posted: the one driven by the FET source feeding the R17/R23 etc. RC network where U1A is acting as an inverting amplifier, and possibly some kind of integrator network off page used to generate the bias voltage for the FET gate.

I'm assuming the goal here is to build a low-noise source follower, with the output buffered by an op amp.

It looks like the non-inverting input of U1A is tied to a virtual ground, and the inverting input is tied to the collector of Q3, I'm guessing to try to use negative feedback to fix the collector voltage at

4.57. But since Q3 is fed by current source Q2, the collector of Q3 (test point P3) is a high-impedance node and so it seems to me that the only way the DC voltage there can be controlled is by U1A sensing the source voltage of the FET, through the R17/R23 network, and then around the loop through the integrator (not shown) back to the gate of the FET, if I'm understanding the circuit correctly.

The gain from the gate of the cascoded FET to the output of U1A isn't well-defined; from "its perspective" it looks like a current source loaded common-emitter amplifier feeding a transimpedance converter. It will be very large. Plus the phase shift from U1A and the integrator to the gate it sounds like a recipe for oscillation.

If I were dead-set on using a current source for the cascode collector load I think it would be better to let one op-amp section handle a feedback loop around the upper current source to set the DC bias at Q3's collector, and let U1A and the integrator just handle setting the FET's bias and the 0V DC level to the post amplifier. Delegate some responsibility...

Reply to
bitrex

Should be "from the gate of the FET to the output of U1A via the collector of the cascode"

Reply to
bitrex

The 17.6pF cap could perform better if it had a flag in the Borussia Dortmund colors black and yellow :-)

Just curious, shouldn't there be a cap to ground at the base of Q3 and maybe also Q2?

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Regards, Joerg 

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Reply to
Joerg

I think you could safely add a little resistance in Q3's emitter. BTW, while studying the Zin scene, you can make changes that would damage the noise performance, just saying.

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 Thanks, 
    - Win
Reply to
Winfield Hill

If you have a chance could you confirm and/or deny that there might be a problem with the feedback connection from Q3's collector to U1A? It looks that way to me or else I'm not understanding correctly how this circuit is supposed to work, which is entirely possible given it's still before noon ;-)

Reply to
bitrex

On a sunny day (Mon, 29 May 2017 11:20:44 -0400) it happened bitrex wrote in :

I looked at it twice and declined to comment as I

1) have no idea what it does. 2) have no idea what it is supposed to do. 3) have no idea why make a peeseebee for something that one has not tested. 4) looks overly complicatiaotiantiated to me, brain abort.
Reply to
Jan Panteltje

Yeah, this is why I don't feel too bad if my suggestion wasn't on the mark.

I know I'm guilty of this myself sometimes, but while people are very familiar with their own designs I don't think everyone else can immediately intuit what's going on in a circuit that has say, more than a couple transistors or op amps. A few sentences of explanation of what's _supposed_ to happen would help OP a lot before jumping right into what the problems are with...whatever it is.

My impression was that it's a cascode source follower with U1A acting as a post amplifier, then feeding an integrator which then feeds the FET gate resistor. Holding the collector of the top cascode transistor at virtual ground by tying it to the op amp inverting input is clever, but it also seems sketchy as the only way U1A has to hold it there is around the loop to the FET gate. Transimpedance amp-connected op amp -> integrator is at least 270 degrees of phase shift at high frequency right off the bat. Seems sketch.

Reply to
bitrex

Bleep! Bleep! Jan Panteltje brain abort! Bleep!

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 Thanks, 
    - Win
Reply to
Winfield Hill

Unless one is willing to grunge through all the math to make sure everything works out then IMO feedback loops around stuff need to be super-tight and encompass the bare minimum of stages. Just wrapping stuff around stuff and assuming it will all work out because the ideal op amp equations say this voltage must be equal to this voltage in a negative feedback configuration is asking for trouble - even if the feedback loop is only "designed" to operate at DC.

Reply to
bitrex

On a sunny day (29 May 2017 08:46:13 -0700) it happened Winfield Hill wrote in :

The real Art is Simple City, ehh simplicity. :-)

Reply to
Jan Panteltje

On a sunny day (Mon, 29 May 2017 11:44:20 -0400) it happened bitrex wrote in :

Yes, and there is more we need to know, drive impedance, requirements, I posted long ago here about my (accidently discovered) better alternative vidicon preamp (better than the common bootstrap circuit). It all depends...

Reply to
Jan Panteltje

+1 on Q3. I'd suggest moving the aptly-named C666 to Q3's base. Current-source Q2 is bypassed to +10V, so no problem there.

I don't trust 2.7V zeners or emitter-followers with big base resistors here. Moving C666 should reveal whether this node is the source of the weirdness.

Cheers, James Arthur

Reply to
dagmargoodboat

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