Routing sense lines of power supplies

Just a CAD tool survey... Is there a tool that understands that there can be a line on a power net that's actually meant to not connect to any other part of the same net? (except on the pin of the sense line) I use Allegro and I manually add no_shape_connect properties to vias so that the sense line can route back to the supply without shorting to the power plane. This seems silly.

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Why is that an issue? I'd never let my layouter hit the autorouter button for stuff like that. This needs to be hand-routed anyhow IMHO.

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Regards, Joerg

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Joerg

Hello, What I do in Altium Designer when I want to do an auto route is to define a dummy component in schematics(eg. a 0402 SMD resistor) and connect the sense line to that resistor so it has a separate net. At time of assembly it can be easily short circuited with a drop of solder.

Regards, Ebrahim

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Ebrahim

PCAD200x (now deceased), Pulsonix - read about "start point" in the documentation. I would expect any half-reasonable CAD have similar options.

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Andrew
Reply to
Andrew

I believe you mean, "star point."

If someone knows how to do it in ORCAD C(r)apture, I'd love to know how. We typically use the zero-ohm resistor trick instead.

---Joel

Reply to
Joel Koltner

Sense lines function on the basis of current flow through differing micro-impedance tracing. This can be simplifiedfor CAD by introducing an identifiable component, be it a low value resistor, link or other physical object.

As practical remote sense lines may need an alternate remote connection point, this isolating lower-impedance element is often required anyways as a 'default' connection, in the event of an open-circuit remote connection.

RL

Reply to
legg

But that open circuit protector goes from sense to power trace, not in series with the sense trace. So the sense trace is still the same node as the power trace unless you put something in series as well, which seems to be what the OP doesn't want to have to do anymore.

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Regards, Joerg

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Joerg

For simple single-fault abnormal ruggedness, any sense tracking should have an identifiable impedance that can limit fault currents to some level of survivability, if not repairability, for the duration of the fault/protection interval. Simple tracking is unlikely to do this.

Open circuit board traces are not an acceptable result of a single fault abnormal test in safety certification, regardless of their location in the product. The cost is therefore easily justifiable in any power circuit application requiring a safety certification.

RL

Reply to
legg

Hmm, interesting, they never made us do that. But it does make sense in situations where the proverbial wrench could fall into the unit. Or wedding band etc. ... bzzzt ... *phoof*. Although that's not S.F.C. in most gear because there is an enclosure.

Usually there is some sort of opamp input at the other end. When that shorts out that part of the opamp just dies. The series resistor wouldn't keep it from dying because that would be where the fault started anyhow.

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Joerg

Fault duration and performance for survivability anticipates the circuit single-fault behaviour, the fault protection processes that are provided and the end result. All that the limiting impedance does is to protect the board trace during this period - it does not guarantee equipment operating integrity or single-fault performance: that is for the designer to anticipate and to prove in the normal process of product design and development.

Open board traces resulting from a single fault is a non-starter.

RL

Reply to
legg

Express PCB doesn't care. You put the traces where you need them and check your work carefully

Reply to
MooseFET

Ok, I have thought about this for a few minutes, and I think you are wrong.

You see, if you are dealing in CAD, then, the net is the net. Everything in that net is equal, and it is how things are tracked and set up in the software. What you want, is for the trace to be the trace. You want a sub-net of a net to be different from the net. To do this, you need to give it a name different from the net, which means it is a different net! There is no logical way around this. PWR_SENSE should be a separate net, with its own rules, and not considered part of the power net.

If you really don't like having a zero ohm resistor, create a new part SHORT that consists of two small SMT pads connected by a section of trace. Will do what you want just fine!

Charlie

Reply to
Charlie E.

Sure! No reason at all that a trace can't be defined as a part.

...Jim Thompson

--
| James E.Thompson, P.E.                           |    mens     |
| Analog Innovations, Inc.                         |     et      |
| Analog/Mixed-Signal ASIC\'s and Discrete Systems  |    manus    |
| Phoenix, Arizona  85048    Skype: Contacts Only  |             |
| Voice:(480)460-2350  Fax: Available upon request |  Brass Rat  |
| E-mail Icon at http://www.analog-innovations.com |    1962     |
             
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Reply to
Jim Thompson

T'is how it's done. However, it does show up as a part in the schematic. So you end up with two sets of schematic. One for the netlist generation and another for the ECO release. Not cool.

I've never tried but I believe in Cadsoft Eagle you can define a part that looks like a piece of wire in the schematic with suppressed P/N and designator. So you wouldn't even see it later. A downside is that you shouldn't change the wire width in the schematic or that area will look swollen or indented, unless you create library "shorting parts" for various line width. Name them something really odd, such as "REMOVE". Then you can write a ULP routine that weeds out such parts. Not sure if other CAD systems can do that.

I usually ask the layouter to route those things by hand. Typically he has to hand-route analog areas anyhow so it isn't any extra work for him.

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Reply to
Joerg

[snip]

I do it all the time in my microchip designs... schematic notations that keep the layout guys doing what I want, yet, when net-listed, it's all one net... one benefit of using the original MicroSim Schematics... multiple template capability ;-)

...Jim Thompson

--
| James E.Thompson, P.E.                           |    mens     |
| Analog Innovations, Inc.                         |     et      |
| Analog/Mixed-Signal ASIC\'s and Discrete Systems  |    manus    |
| Phoenix, Arizona  85048    Skype: Contacts Only  |             |
| Voice:(480)460-2350  Fax: Available upon request |  Brass Rat  |
| E-mail Icon at http://www.analog-innovations.com |    1962     |

Leftist weenies think that Letterman is hilarious with a degrading
"joke" about Palin\'s teenaged daughters.  Wonder how funny they\'d
find it if Letterman said something like, "Michelle Obama has a
big butt and a face to match" ???

I think that\'s a VERY funny "joke" ;-)
Reply to
Jim Thompson

In medical and some other markets one is more restricted as a circuit level designer. Monsieur l'inspecteur does not like it when there are hand-edits in schematics after things like netlists are generated. Sure, it can all be properly documented but often this isn't considered kosher among people.

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Regards, Joerg

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Joerg

"Hand-edits"?? Who said anything about "hand-edits"? It's all automagical ;-)

Schematic appearance and netlisting are two different animals... two or more... in some cases I have FOUR automagical netlist types ;-)

...Jim Thompson

--
| James E.Thompson, P.E.                           |    mens     |
| Analog Innovations, Inc.                         |     et      |
| Analog/Mixed-Signal ASIC\'s and Discrete Systems  |    manus    |
| Phoenix, Arizona  85048    Skype: Contacts Only  |             |
| Voice:(480)460-2350  Fax: Available upon request |  Brass Rat  |
| E-mail Icon at http://www.analog-innovations.com |    1962     |

Leftist weenies think that Letterman is hilarious with a degrading
"joke" about Palin\'s teenaged daughters.  Wonder how funny they\'d
find it if Letterman said something like, "Michelle Obama has a
big butt and a face to match" ???

I think that\'s a VERY funny "joke" ;-)
Reply to
Jim Thompson

Well, in some of the areas where I work you better make that "one" :-))

But chip guys have a whole lot more liberty here.

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Regards, Joerg

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Reply to
Joerg

This is precisely why Pulsonix (and I have to assume other packages) have "star points" and other part categories that specifically don't produce BOM entries. (They can go the other way too, having "associated parts" where one part can create multiple BOM entries... this is ostensibly used for, e.g., heatsinks that you always use with a given part or other mounting hardware or whatever, but truth be told I've never used one particular heat sink or mounting hardware so close to 100% of the time to find it useful.)

---Joel

Reply to
Joel Koltner

"Jim Thompson"

Good DRC checks all copper that will end up in the gerber and flag an error.

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Andrew
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Andrew

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