I should know this, but it's easy to ask.
Assume the rising edge of a pulse that is delayed from a trigger, and that has 1 ns p-p jitter relative to trigger, with a uniform probability distribution. We'd get that if we used a 1 GHz unsynchronized clock to generate the delay, which we're now doing in an FPGA.
What is the RMS jitter? I recall there being something like a square root of 12 in there somewhere.