replacing the seven segment decoder/driver with a pal+latch

You're a little unclear on what you're doing, normally the PAL would be sufficient to replace a decoder/driver if TTL levels out are good enough and you wouldn't need the latch.

Do you have a microcontroller anywhere there?

Using shift-register drivers (like HC595's or their power-driver equivalent) lets you avoid a decoder chip of any kind, and you only need three pins out of your microcontroller (some of which you may be able to share with other functions) to drive as many digits as you like.

Tim.

Reply to
Tim Shoppa
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I am designing a circuit that will use the seven segment LED display for output.

I dont have the decoder driver chip and dont want to buy it.

I do have lots of 22v10' and 573/373' (I hate the latters pin out).

Can I decode on the 22v10 ... feed its output to a 573/373 and then to the seven segment LED display?

Would fan out be an issue?

I suppose I should just test it ... when I get home, but I have already started the PCB and nearly done ...

Reply to
samIam

Absolutely!

YES YES I totally forgot (banging head against wall).

I am stuck in 16L* land. Originally I was going to do the decode driver in a 16L8 with 573/373 ...

Forgot to "resync" my thinking when I pickeup the 22v10's.

Good point thanks. I love this newsgroup :)

Reply to
samIam

I assume this is a one-off project.

What's the 573/373 for? The 22V10 contains flip-flops.

Lattice GAL22V10 outputs can sink 16mA. That's enough for an LED segment.

Reply to
Andrew Holme

I implemented this 'font' in my clock project (Moto 68HC908). Its actually quite readable.

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My only comment about 22V10s as decoder/drivers is if you use 1 for each digit, they're kind of power hungry.

GG

Reply to
Glenn Gundlach

Well, the newsgroup loves smart questions like this. As a matter of fact, you've got me thinking of doing a BCD-7-segment in some kind of PLD. I've also seen this pattern (or something very similar) for Sexydecimal ;-) _ _ _ _ _ _ _ _ _ _ _ _ | | | _| _| |_| |_ |_ | |_| |_| _| |_ | _| |_ |_ |_| | |_ _| | _| |_| | |_| _| |_| |_| |_ |_| |_ |

Cheers! Rich

Reply to
Rich Grise

Below is to be preferred: _ _ _ _ _ _ _ _ _ _ _ _ | | | _| _| |_| |_ |_ | |_| |_| |_| |_ | _| |_ |_ |_| | |_ _| | _| |_| | |_| _| | | |_| |_ |_| |_ |

Best regards, Spehro Pefhany

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"it\'s the network..."                          "The Journey is the reward"
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Reply to
Spehro Pefhany

On Wed, 07 Dec 2005 22:55:58 -0500, Spehro Pefhany wrote: ...

OK, you're right, that is better than mine. :-)

(but I _did_ kind of make it up on the fly. :-) )

Thanks! Rich

Reply to
Rich Grise

...

...

Speaking of LUTs, what ever happened to the 8223, 32X8 PROM? They were handier than a rat for a universal 5-input, 8-output thing. Yes, that's thirty-two by eight - thirty-two eight-bit bytes. Maybe these days they're just using SOIC OTP 27512s or something?

Thanks, Rich

Reply to
Rich Grise

Too small to bother with. Even 64Kx16 is too small. Use a PLD of some sort.

--
  Keith
Reply to
Keith Williams

Here's some simple VHDL code for a 7-segment decoder as above, with segments inverted to drive a common-anode display (written by David Warren-Smith). Note that VHDL isn't case-sensitive, so D==d, S==s, SEG7==seg7:

LIBRARY ieee; USE ieee.std_logic_1164.all;

-- Title "7 segment display driver circuit";

-- File: seg7.vhd

ENTITY seg7 IS PORT (D : IN STD_LOGIC_VECTOR (3 DOWNTO 0); -- BCD input S : OUT STD_LOGIC_VECTOR (6 DOWNTO 0)); -- 7 segment outputs END seg7;

ARCHITECTURE display OF SEG7 IS BEGIN s

Reply to
Spehro Pefhany

In article , Spehro Pefhany wrote: [....]

I have found that it is better to make the names of ENTITYs and ARCHITECTUREs more obvious such as:

ENTITY SevenSegmentConnect IS and ARCHITECTURE SevenSegmentDisplay OF SevenSegmentConnect IS

It doesn't matter in a simple case like this but when you have a hundred or so of each, remembering what matches up with who can be troublesome.

--
--
kensmith@rahul.net   forging knowledge
Reply to
Ken Smith

The equivalent function, but I've found that a process using case/when often produces better logic:

LIBRARY ieee; USE ieee.std_logic_1164.all;

-- Title "7 segment display driver circuit";

-- File: seg7.vhd

ENTITY seg7 IS PORT (d : IN STD_LOGIC_VECTOR (3 DOWNTO 0); -- BCD input d : OUT STD_LOGIC_VECTOR (6 DOWNTO 0)); -- 7 segment END seg7;

ARCHITECTURE display OF SEG7 IS BEGIN

seg7: PROCESS (d) BEGIN CASE d IS WHEN "0000" => s s s s s s s s s s s s s s s s NULL; END CASE; END PROCESS; END display;

Synthesizers are template driven and I've seen if/elsif/elsif/... and when/else/when/else/... produce some terribly serial logic. At least with Synplify the case/when template is often a lot cleaner.

--
  Keith
Reply to
Keith

I find your method to be awkward when trying to follow or scope a signal through many levels of herarchy. The names get to be unmanageable.

--
  Keith
Reply to
Keith

Humm... I tried both ways, and the Xilinx tools created 4 slices/7 LUTs/3 levels of logic both ways... automatically extracting a 16 x 7 ROM in both cases. For what that's worth.

Thanks for the tip.

Best regards, Spehro Pefhany

--
"it\'s the network..."                          "The Journey is the reward"
speff@interlog.com             Info for manufacturers: http://www.trexon.com
Embedded software/hardware/analog  Info for designers:  http://www.speff.com
Reply to
Spehro Pefhany

In article , Keith wrote: [...]

I don't see how. How does what I've done effect the signal names? I assume you mean that the signal names get unmanageable.

In the tools I've used ( small set I admit ) the names in reports are built up with instance names not the type of the entity so it is the instance name that you want to keep shortish.

--
--
kensmith@rahul.net   forging knowledge
Reply to
Ken Smith

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