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Redundant clock switching

First of all, I was comparing a PFD to a _good_ phase detector (DBM or MUX) and not to an XOR. However, XORs are in fact generally quieter than PFDS.

PFDs have a lot more going on than XORs, which means more jitter and drift, and (unless you're doing something fancy) the servo point is in the middle of a deadband, so it hunts around like a bastard within about a 3-ns window for HCMOS or wider for metal-gate CMOS. The deadband is caused by the output becoming a runt pulse when the timing error is less than the sum of the rise and fall times of the output. The pulse amplitude becomes sensitive to supply variations, small temperature changes, what you had for breakfast, and so on.

The loop filter won't let an XOR lock up on the wrong edge, because the DC feedback is positive there.

Pure nonsense. To even begin to use a PFD with a noisy signal, you have to use a bandpass limiter such as an FM IF strip just to make logic levels. That degrades your SNR by intermodulating all the noise components, which may make locking impossible all by itself. It's also useless for signals where you don't know the centre frequency that accurately.

Also, with a PFD, if you miss a transition due to noise, the loop unlocks and has to re-acquire, whereas an analogue PD or even an XOR just carries on. That alone makes PFDs completely unsuitable for noisy signals. A narrow loop filter is no help whatever for either of these problems--by the time it sees the signal, the damage has already been done.

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs 
Principal Consultant 
ElectroOptical Innovations LLC / Hobbs ElectroOptics 
Optics, Electro-optics, Photonics, Analog Electronics 
Briarcliff Manor NY 10510 

http://electrooptical.net 
http://hobbs-eo.com
Reply to
Phil Hobbs
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You are not working with correction pulses. You are working with square waves.

As JL stated, single-ended CMOS will always be drifty. A 74HC86 is single- ended.

I don't know where JL is talking about differential input/output ECL gates and diffamp-input loop filters. The MC10EL/100EL07 is a 2-input XOR/XNOR gate. It drifts even worse.

Reply to
Steve Wilson

I don't know what you are talking about the retrace. The lock point is the middle of the ramp. It is linear to the edge of the window on both sides. Once you exceed the window, you are out of lock.

The edge of the window is very well controlled. The distance between one window and the next is zero.

I don't know which Motorola pfd's you are talking about. The MC4044 has deadband due to one transistor coming out of saturation slowly. The MC4046 and similar devices have mosfets driving the single output pin. These can be slow. At least one pfd ic allows you to select the delay in the feedback path to help overcome deadband.

Pulling the loop off balance is very poor engineering and badly controlled. It is much easier to simply remove the deadband.

I still don't know what you are talking about with gain asymmetry. There is none with a proper pfd.

Switching the sign of the feedback will cause the loop to rail.

Reply to
Steve Wilson

Not all. <

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> I really like it.

cheers, Gerhard

Reply to
Gerhard Hoffmann

AD9901 is a nice part. It works as a PFD away from lock but XORs when in lock, best of both worlds. And it accepts single-ended or differential inputs.

--

John Larkin         Highland Technology, Inc 

lunatic fringe electronics
Reply to
John Larkin

Any CMOS circuit will have temperature drift, picoseconds or tens of same per degree C. That maps things like air currents into phase noise. CMOS logic levels are also Vcc sensitive and just plain analog noisy. Differential ECL (or a good analog multiplier) is the way to go for low phase noise.

Someone in the time-nuts list independently confirmed our numbers.

I think our methodology is legit. If there were 346 fs of RMS jitter, the step curves would be correspondingly wider.

The measurement stands on it own; we built it and calibrated it and reported what the circuit did.

1 ps RMS jitter would have been fine for our needs; we were suprised by the fs jitter floor, and thought that we would share it. I've done 1 ps jitter PLLs using far slower parts than that flop.

If you think the measurement is wrong, explain why. Using terms like "fooling yourself" and "fraud" is illogical and deliberately obnoxious.

--

John Larkin         Highland Technology, Inc 

lunatic fringe electronics
Reply to
John Larkin

We use the 9901. When the loop is in lock it *is* an XOR. It does amazingly ugly things in PFD mode, out of lock.

We want time locking precision, so we run the differential outputs into a good diffamp.

As Phil notes, an XOR PD can get outside help (easy in an FPGA) to push it into the lock zone, separating the seek and lock functions. I've done that by just switching the loop filter to wideband when I detect loss of lock, but the 9901 does that internally.

--

John Larkin         Highland Technology, Inc 

lunatic fringe electronics
Reply to
John Larkin

So, instead of two states, there's three. Why does that make the symmetry argument on correction times any different? How does 'drift' relate to timing or amplitude of the signal?

Doesn't that indicate that 'single-ended' is not relevant? Are you just repeating lore (aka old wives' tales) or is there a kernel of knowledge hidden here?

Reply to
whit3rd

There is a _huge_ difference between 10K and 100K ECL. With 10K it could easily happen that a board stopped working when its top and bottom half were differently cooled. 100K ECL with its temperature compensation was a completely new game. 100K was fun!

cheers

Gerhard

Reply to
Gerhard Hoffmann

10K was OK in a good design. But FPGAs are now faster internally than ECL, so there's no reason to do a lot of actual logic in ECL.

I still use a bit of EclipsLite and EclipsPlus and Gigacomm logic. For low jitter and drift, differential is best.

--

John Larkin         Highland Technology, Inc 

lunatic fringe electronics
Reply to
John Larkin
A

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lked

tries

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ow

ave a

window and the next is zero.

What do you mean by "window"? If you don't understand the PFD runt-pulse de adband problem, then with all due respect you don't know much about PFDs. I n physical measurements, nothing has a width of zero.

k

The Motorola-specific scheme is the one with two outputs, e.g. the MC145152 synthesizers.

.

So you claim, but can you back that up with anything except name-calling? A nd can you provide a better method for getting rid of the deadband in a 404

6 PD2? I'm all ears.

ching

s

It's a sawtooth, silly. The loop gain is proportional to dV/(d phi), which is dramatically larger on the quasi-vertical side of the waveform (the retr ace).

No, it'll make it oscillate because it'll try to servo around the wrong nul l, where the gain is too high.

Have you built any PLLS lately?

Cheers

Phil Hobbs

Reply to
pcdhobbs

The way you quoted that makes it seem like I wrote it, but I didn't. You and JL both recommend the AD9901. I've never used it myself, but I'll check it out next time I need a fancy PLL.

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs 
Principal Consultant 
ElectroOptical Innovations LLC / Hobbs ElectroOptics 
Optics, Electro-optics, Photonics, Analog Electronics 
Briarcliff Manor NY 10510 

http://electrooptical.net 
http://hobbs-eo.com
Reply to
Phil Hobbs

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