missing chip seems the obvious option. Your 2 other oscillators phase lock it, but if their input ceases to exist it oscillates on its own, preservin g output.
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rd osc is only locked by osc 2 when the phase of the 2 is close. Until that point, osc 3 runs on its own.
sc 3 rules. And all switchovers are smooth
It's proof against failure of osc 1&2. Of course not against osc 3, but tha t one is inside the OP's equipment so can be made to whatever specs he choo ses. I'm not aware of any option that is proof against failure of the final mix/choose/sync device, which is in this case just osc 3.
Ok, that makes sense. But then one starts thinking about what's more reliable, a third oscillator wherever it may be (I believe OP said later that all oscillators would be internal to the widget, not external.) or some async logic.
Uguh. I get the feeling that OP has been thinking about whatever this project is for a very long time
If you need some system to last for the better part of forever instead of trying to make their internal functional blocks ultra-reliable (and expensive) just build 50 cheapos that do the same thing, one of them probably will!
I thought I already explained why a 3rd osc was more reliable.
If you want to go there you could always add a parallel digital only approach designed to output in sync with the analogue osc3, so even if osc3 fails you still get your signal.
I presume the OP will use different types of osc so that as many failure modes as possible only apply to one.
I recently did an oscillator and dual mixer time difference system that was non-redundant because we could not tolerate any 2nd oscillator in that frequency range because they might injection-lock or change their tuning curves. The job was to lock a Space Hydrogen Maser and a Cesium to get both short & long therm stability. Both delivered 100 MHz and were down-converted by 99.99 MHz or so. The phase relationship stays the same, and in absolute ps you see it magnified by 1000. Most of the instability of the 99.99 MHz cancels, but not all. (1)
That was quite some fun to provide enough loop gain without spoiling the phase noise and tuning range WRT aging. That oscillator also drove the clock of the downstream FPGAs, non-starting would have been a complete mission failure.
There was a lot of triple module redundancy in the FPGAs. I decided not to replicate the clock nets, trying that is an invitation to commit a lot of design errors. You have not only to decide if a module is wrong and which one, and then to heal it, but replicating the clock means that you cannot even easily say WHEN the results should be the same. And gating clocks is dirty.
Also, there is no such thing as 3 clock nets in an FPGA. If you think about the buffers that drive the clock segments, there are more like
3*1000 clock nets that may get individual single event upsets. That is no more like 74LS, where CLK was one wire.
TMR is not a cure for everything.
There was a Xilinx app note written by Peter Alfke on glitch-less clock switching. Must have been in the XC4000-era and was quite convincing IIRC.
Oh, and crystal aging is easy to spot. That's when you try to lock to a carrier and Vtune approaches VCC or VEE. It never used to do that! ;-)
cheers, Gerhard
(1) The cause for the incomplete canceling is that you measure the time difference between the two channels. But the phase noise is not completely the same at the 2 sample points involved.
I don't care about the aging-induced frequency shift, absolute accuracy is not critical for my purposes. The absence of the DC generation mode is, though. ;-)
A good point. IMHO the PLL cleanup block should be pretty immune to the last stages of crystal dying.
Here I plan to start. But one never knows how hi-rel is hi-rel, so I wanted to add this last resort failover mechanism. I'm afraid that two oscillators from the same manufacturer can exhibit similar failure modes, so the plan is to use a crystal and a MEMS at once and let them play their ordeal.
I'm not so sure. Let's say each oscillator output is fed through a resonant LC filter or similar, then they're either working ok or no output is prese nt. (Yes there are other possibles, but that knocks out 99% of wrong freque ncy output.) Now sum all those outputs & feed them back to each oscillator to pull it into line. You now have effective redundancy.
None last forever. You can only figure out & pick the best you can come up with.
In my observations of hi-rel goods, most fail due to some weak spot that wa sn't as reliable as the rest of the thing. The same pattern occurs in domes tic goods, albeit at a much lower reliability & price point. Most of an ite m might be built adequately but there's nearly always a weakspot somewhere.
And it can be surprising what turns out to be most reliable. Often it's old kit that was never built to great reliability standards, yet outlasts the modern stuff anyway.
The last claims greater than 1000 million hours MTBF. Hype? Probably some in there but with a mems osc your PLL clean up block may have a higher failure rate.
The weak spot in men's leather belts is the holes. So do away with the holes:
The weak spot in these belts is the tooth and lever mechanism that clamps the buckle on to one end of the belt. The teeth gripping into the leather gradually produces wear and eventually friction isn't enough to hold the buckle on and it falls off. Have to cut a bit of the end off to get to a fresh section of leather and re-attach, so the belt gradually becomes shorter with time. It helps belt longevity if you're on a diet and losing weight concurrently with this happening.
Are you proposing to have two of your own oscillators, and switch if one fails? Most XOs these days are an IC and a piece of quartz, so the switchover circuit could be less reliable than one XO.
If you really need to switch sources, something really simple like a
1-transistor injection-locked oscillator could follow a simple mux, and make an always-on, glitch-free handoff.
--
John Larkin Highland Technology, Inc
picosecond timing precision measurement
jlarkin att highlandtechnology dott com
http://www.highlandtechnology.com
If they're all cheap, they'll all have 85C electros in them. :(
Cheers
Phil Hobbs
--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC / Hobbs ElectroOptics
Optics, Electro-optics, Photonics, Analog Electronics
Briarcliff Manor NY 10510
http://electrooptical.net
http://hobbs-eo.com
But even with a hype derating factor of 10 that makes them better than the best crystal oscillators.
Yes, with suchan amazing FIT any form of redundancy circuitry is likely to spoil the overall reliability. And the chips are easily available. Thanks, Joe, the data you have provided close the case.
"own" = an unit from the shelf, there is no point in making a custom XO, maybe except of the most extreme cases. But yes, that's exactly the idea.
The crystals do fail. Rarely, but they do. One of the main causes is improper thermal stress relieve mechanism, which breaks the glass sealing and make the suspension corrode. Hence my concerns.
A dirty approach would be to resistor-sum two oscillators' outputs, one with a large resistor (the backup) one with a small resistor (the master). Phase-lock to the sum, using AC coupling, with an XOR-type phase detector. For extra jitter rejection, a bit of hysteresis on the phase detector input would help. Biggest signal wins!
A fast '4046 variant could handle it straight up, and if the phase glitch on turnover is an issue, you could cascade two PLLs and let the loop filter ease the output transition. The nice thing about jelly-bean chips is... they're economical even with quick 'n dirty engineering.
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