Really triangular triangles

Hi all,

So I have this nice 1 nA/100 MHz shot noise limited front end mostly designed. I can't post the schematic due to NDA issues, but the basic idea is to use an Avago ATF38143 pHEMT running common-source, with a BFP640FESD SiGe:C BJT as the cascode. Thanks to the gigantic Early voltage of the BFP640F, the front end runs at a DC gain of about 32, and goes into a THS3091 CFA with a gain of +10. A 10-ohm bead in series with its base keeps the BJT from singing at 6 GHz, which it otherwise will.

There's a current feedback loop that uses a 100 meg feedback resistor to stabilize the operating current of the front end. It rolls off at around 10 kHz.

A current pulse at the input causes the ~0.8 pF input capacitance to charge up, which produces a ramp at the first stage output. This gets differentiated by a parallel RC to produce a nice pulse output again.

100 MHz bandwidth, no overshoot, nice 3.5 ns edges, even with reasonably realistic board strays included.

The bad news is that the time constants have to be right, which means they have to be tweaked.

The high frequency gain is proportional to 1/C_in, so the low frequency gain has to be tweaked to match, once the sample is attached. In addition, the bias and differentiator TCs have to match, though those don't have to be tweaked for each sample. So it needs two production tweaks and one user tweak, about like a scope probe.

To save wear and tear on the users, I want to put in a good self-calibration signal so that they can tweak it easily. The three tweaks all have quite different TCs, so it isn't hard to get right--just go in order from slowest to fastest, then repeat, and you're done.

However, since the input is 0.8 pF // 100 meg, I can't connect anything to it to do the calibration, which is a problem.

I'm planning to use an asymmetrical ramp generator connected to a pad near the input node, so that I get about 0.05 pF of coupling. At that point, a ramp of 0.2 V/us will give me 10 nA of input current, which is a convenient number. A volt peak to peak is fine.

However, I really want the pulse tops flat and the edges square (ideally

1 ns or faster) so that we can really test the full performance of the gizmo--in other words, I need a really triangular triangle wave generator.

The good news is that it doesn't have to drive anything much--just its own output trace--and that the ramp is pretty slow, so I can use a big high voltage NPO integration cap to swamp out the nonlinear capacitances of the active devices--1 mA into 4700 pF @ 100V, or something like that.

The bad news is that I don't get to wring this board out myself, so it also has to be reasonably idiot-resistant. (My customers are very smart people, but they aren't circuits folks, and I don't know what their in-house EE support looks like.)

Any wisdom?

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs
Principal Consultant
 Click to see the full signature
Reply to
Phil Hobbs
Loading thread data ...

I recall a Tektronix appnote or something, where that lamanted the quality of capacitors, intentional and otherwise, made of FR4. They have "hook", which I guess translates to lots of dielectric absorption or c-vs-f or something. FR4 has a ghastly capacitance TC, too, numbers like 900 ppm/K. Are you using some fancier laminate?

Can you use air? Like a wire or plate bridge over your input node.

You can make a very linear ramp in your speed range with a simple closed-loop current source feeding a good cap through a ferrite bead. I make ramps that are 10 and 12-bit linear, numbers like 100 volts/us.

0.2 v/us should be easy. Given that, you could go to a very small value air cap and ramp harder.

What's the parasitic capacitance of that 100M resistor?

--
John Larkin                  Highland Technology Inc
www.highlandtechnology.com   jlarkin at highlandtechnology dot com   
 Click to see the full signature
Reply to
John Larkin

I'm assuming about 0.1 pF--that's one of the TCs, but any variations there are tweaked out by the other adjustments.

Just making the ramp is a piece of cake with an integrator + Schmitt, but even with an ECL or LVDS comparator, I sort of doubt I'll get 1 ns corners with any reasonable op amp--though maybe I could use that nice ADA4899 of yours. Good corners will be a big help, because due to the weird input specs I can't readily hang a pulser on the input, and it would be nice for the customer to see that it does what I say it will.

Re the capacitor: I remember the "hook" app note, and although hook is mostly a >1GHz issue, since I'm looking for something pretty, I'd probably have to worry about that. I was considering using some nice Rogers material on account of the temperature and humidity problem, but the air bridge cap idea is a good one--I'll need some electrostatic shielding anyway, so perhaps I can use one of those little cell phone shield cans, and drive that. The capacitance would be easier to calculate, that's for sure, and if all else fails I can measure it. Might be a good excuse to get a copy of FastCap.

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs
Principal Consultant
 Click to see the full signature
Reply to
Phil Hobbs

Somebody, IRC maybe, makes a surface-mount manganin shunt resistor that - cool - looks like an Omega. That could hop right over your signal node and be the shield/cap. And Fotofab will make any shield you want.

--
John Larkin         Highland Technology, Inc

jlarkin at highlandtechnology dot com
 Click to see the full signature
Reply to
John Larkin

Interesting. Wouldn't any surface mount resistor suffice though? Or is the ceramic carrier a bad dielectric?

--
Failure does not prove something is impossible, failure simply
indicates you are not using the right tools...
 Click to see the full signature
Reply to
Nico Coesel

How long are your time constants? IOW how long do you want your pulse to be, or how much amplitude does you saw tooth need to be? Did you really mean 100V excursion? That'll be pretty tough with your 1ns requirement.

--
Thanks,
Fred.
Reply to
Fred Bartoli

Speaking of phemts and singing and stuff, I did this fast pulse generator that uses a linear ramp and a couple of comparators to make a delay-and-width thing. It has three ramp ranges, 2.5/25/250 ns. I use an NE3509 phemt to discharge the ramp; we discussed the gate level shifter here a while back. The gate is driven by an EclipsPlus flipflop.

Well, it worked like hell. There was ringing all over the place, multiple edges, weird nastiness. I guess the phemt was turning on too fast, too hard, maybe oscillating a bit. So I stuck a 1.2K 0402 resistor in the gate, and now it's beautiful.

formatting link

What a pain. It took me a half hour or so to hack that resistor in.

Surprisingly, the overall insertion delay of the gadget didn't change enough to notice.

formatting link

formatting link

--
John Larkin         Highland Technology, Inc

jlarkin at highlandtechnology dot com
 Click to see the full signature
Reply to
John Larkin

Alumina has an effective dielectric constant of about 10, so any variation in the resistor's height above the board, due e.g. to different solder volume, translates into a big capacitance variation.

I think I found the ones John is talking about,

formatting link
. The capacitance would be in the right range, but I'd have to put an extra quarter inch worth of trace on the front end, which I'd rather avoid.

I might use one of the nice little poptop shields from Laird, e.g.

formatting link
, which have gaps where I can escape the signal traces on Layer 1.

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs
Principal Consultant
 Click to see the full signature
Reply to
Phil Hobbs

No, a volt or so would be fine, i.e. a 5 us ramp at 0.2 V/us, but it needs to be asymmetrical so as to have long enough recovery time for the tails at different time constants to look different. Something like 5 us up / 50 us down would be ideal.

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs
Principal Consultant
 Click to see the full signature
Reply to
Phil Hobbs

Interesting. So maybe a differential-output ECL comparator driving a pHEMT diff pair, with a couple of current sources and several NPO caps from the outside of the shield to ground, doubling as RF bypasses.

I have bipolar supplies, so that's not too hard to do on the sink side. All I need then is a stiff, high-Z current source with good transient response. (Unfortunately all the good transistors are NPN or N-channel.) Maybe one of your op amp + flying voltage reference gizmos, with one of those nice Coilcraft BCR conical inductors in series to improve the corners. (It wouldn't really need anything that good, but I've been wanting an excuse to try them, and they'd certainly do the job.)

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs
Principal Consultant
 Click to see the full signature
Reply to
Phil Hobbs

AFAIU you want to match the gain of a low frequency path to a high frequency path. Can't you just use a generator that sends out two or more frequencies? Save you the expensive opamps and whatnot in a fast ramperoo circuit.

If it really has to be ramps and you need opamps, consider these:

formatting link

I suggested them to a client for a fast fiberoptics thing and it blew their socks off. Of course, doing the layout is like driving a souped-up Porsche on a sheet of ice.

--
Regards, Joerg

http://www.analogconsultants.com/
Reply to
Joerg

But the void is not alumina, rather air (e=1).

Huh, I just put a few of those in a design but had never seen even a picture of one before. I thought they'd just look like a regular SMT resistor.

Neat. I could have used those in a previous life. The CPoE has custom shields made.

Reply to
krw

That sounds pretty good. All those caps would keep ringing down. I have another driver idea that I'll email to you.

I really would like a good "output stage" like that, namely a phemt diff pair, current-steering mode, programmable amplitude and DC offset. I tried it a couple of times and made oscillators. Discretes are maybe just too big, with too much parasitic inductance, to work. I do intend to try again soon.

The conicals are impressive, but they are wound with, like, #40 wire, so they are delicate and hard to handle. Several people make them now... I guess the Piconics patents timed out.

Some day I'd like to make a benchtop pulse generator, something to compete with the Agilent and PSPL boxes.

Check the price on this:

formatting link

It only puts out 2 volts p-p, with 60 ps edges.

--
John Larkin                  Highland Technology Inc
www.highlandtechnology.com   jlarkin at highlandtechnology dot com   
 Click to see the full signature
Reply to
John Larkin

and

Right. It works like a gap in a ferrite core, so variations in its thickness get multiplied by 10 when computing the variation in capacitance.

I could do that too, but I'm not a mechanical CAD guy, and this is a lab gizmo (a front end for a biochip for DNA sequencing).

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs
Principal Consultant
 Click to see the full signature
Reply to
Phil Hobbs

Yeeouch, $80k! I get better edges than that with an SD-24 and a Mini Circuits RF amp. Makes a great laser driver for lab purposes.

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs
Principal Consultant
 Click to see the full signature
Reply to
Phil Hobbs

This is a research project for DNA sequencing, so parts cost is almost irrelevant. Plus the step response is a key parameter, and (owing to the weird input specs) would be very difficult for non-circuits folks to measure accurately. I'm completely happy for the BIST to cost $50 per board if necessary.

I can easily imagine. Since I don't get to supervise the layout, something slightly tamer would probably be best. Nice part though.

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs
Principal Consultant
 Click to see the full signature
Reply to
Phil Hobbs

A frequency domain measurement with fat amplitudes can ascertain time domain parameters as well. I was just thinking about what might be easier, not cheaper. But if you ramp gen works, then yeah, why not?

On this kind of project I'd insist on checking off the layout. Unless there is a hardcore RF guy doing the layout on their side a major screw-up would almost be guaranteed otherwise.

--
Regards, Joerg

http://www.analogconsultants.com/
Reply to
Joerg

In a manner of speaking.. To be precise, total capacitance / inductance (as effective air length) looks like 1 / (l_e/mu + w) where l_e is path length in the medium (thickness of alumina / length of core), mu is perm(ittivity/eability) and w is the air gap length. The factor of ten is in comparing the lengths to each other, but not necessarily the total capacitance or sensitivity (when gap is very small, C ~ constant; when gap is larger, C ~ 1/w).

Yet another possibility: print a couple PCBs and stack them as shielding. Top of the stack is a solid ground plane, with pads around the periphery to stitch it. Middle layers are "hollow" boards, which can be easily made by routing out most of the area, providing clearance for components. These also get pads around the perimeter.

You could make symmetrical stripline this way, by sandwiching the main board (with solid ground plane on the back, and signal/components on the top) against another (with just a ground plane, and lots of vias to stitch it, and routes to provide clearance for components). The boards could even be epoxied together to fill the air gap.

All these things with PCBs have the same awful tempco, which isn't necessarily a bad thing if you can compensate with the same or an equivalent tempco...

Tim

--
Deep Friar: a very philosophical monk.
Website: http://webpages.charter.net/dawill/tmoranwms
Reply to
Tim Williams

All the plots I'm giving them are time-domain and SNR, and with the ramp generator they can see if the tweaked system gives them the results they expect. It's a nice clean demarcation, which is important when your customer is 14 time zones ahead of you. ;)

Yup. I'll get them to send it to me to look at, but I have no idea if their layout guy speaks good enough English for us to communicate.

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs
Principal Consultant
 Click to see the full signature
Reply to
Phil Hobbs

[...]

BT. While in Seoul on a noise debug mission one of the engineers asked me: "What leeshe fuh hey oy won glou in shiste?"

Translating to English English: "What is the reason for having only one ground in the system?"

--
Regards, Joerg

http://www.analogconsultants.com/
Reply to
Joerg

ElectronDepot website is not affiliated with any of the manufacturers or service providers discussed here. All logos and trade names are the property of their respective owners.