Can we have flip-flops that are triggered by both positive and negative edges of clock (instead of the regular ones that are triggered only on a single edge of the clock)? If yes, then why are these not usually used?
Thanks!
It's easier to use a regular flop clocked at twice the speed.
I know, but the reason why I posted this question is because I have a clock with a fixed frequency and my state machine needs to change state at double the clock rate. Any solution for this? If the answer is by using a clock frequency doubler, then is there a simple circuit for that?
In any case, I would still be interested to know if using both edges of clock to trigger a flip-flop is a bad idea, and why so.
Flip Flops are bi stable switches that are handy for frequency division. You could make one clock with both polarities, but why would you? What purpose does that serve?
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Because it is easier to double the speed of the clock by feeding the clock and a delayed version of the clock waveform into an exclusive-OR gate.
It isn't usually done because the mark-to-space ratios of clcock waveforms aren't all that tightly specified, so the interval between clock edges of the doubled-frequency clock ends up with a rather large worst-case tolerance.
-- Bill Sloman, Nijmegen
There's the right way, with a PLL, and the simpler but kludgy way with a one-shot, or an xor gate and a little delay. Let us know how many parts you can afford to do this.
You're f****ng lucky you get edge triggered ones without having to bother about shit like that. Fucking hell, if you had to bother about shit like that then all the shit you designed would be f****ng shit. Fuck me..... I'm glad I'm not bothered about f****ng shit like that.
Next thing you'll be asking about n-dimensional relational data bases and how to store them on hard disks in sequential space.
DNA
Non-sequential space, please ;-)
...Jim Thompson
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I love to cook with wine. Sometimes I even put it in the food.
What clock rate and logic technology are you working with?
What kind of state machine is this, how fast, and on what kind of logic is it implemented ? Is there any way to redesign the state machine so it doesn't need to change state at twice the clock rate ?
The state machine is for implementing a circuit that will divide a given clock frequency by, say, 3. I was only interested in creating a HDL design for it. I'm not going to map it to actual hardware. But yes, there is one solution that doesn't need twice the clock rate; another one does.
Aha. The best way is to avoid doing it, by using the regular clock, and an enable signal that's only high every 3rd clock.
Alternatively, if you really need a /3 clock, but don't care about the duty cycle you can use that enable signal as the clock, as long as it's glitch free.
50% duty cycle divide by 3 clocks can be made by various clever tricks. This pdf shows one on page 2.Instead of using a flipflop that clocks on both edges, it uses a regular flipflop with an inverted clock.
If you need this stuff on an FPGA, pick one that has dedicated hardware for manipulating clocks, such as a DCM module.
Pretty please. A couple of 44-gallon drums of non-sequential space is just what I need for my teleportation machine.
-- Bill Sloman, Nijmegen
Several suggestions: Make a 2X clock. There are lots of clock-buffer PLL chips available. Use the other edge on a few FFs. Standard state-machine tools probably won't help. Use the async reset input. Rearrange the problem so you don't need both edges. Kludge something with gates.
It's possible to make one, but it would cost more and it would probably run quite a bit slower. There probably isn't much of a market for it.
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DDR RAM uses both clock edges. There is no fundamental reason why the usual flip-flops don't. It's just not done.
The subject of dividing by three comes up regularly. Just google around a bit and you'll find several. Perhaps there would be a market for a chip that does so. Another TinyLogic chip or some such.
Jeroen Belleman
There are some good reasons, though. If the design is limited by combinatorical delays, such as typically the case in an ASIC or FPGA, using a double edge flip flop will reduce your timing budget if you cannot guarantee a perfect 50% duty-cycle, symmetrical thresholds, and equal setup/hold times for both edges.
A double edge flip flop can be useful in bandwidth limited designs, such as external DDR RAM interface, where it will allow a greater throughput. In this case, the double edge flip flops are only used in the interface logic. Internally, the data is processed on a higher clock, or using 2 bits in parallel.
ve
Its bad because it serves no function, you would get the same out as you put in.
Or its inverse, depending on the luck of the draw. ;-)
Cheers! Rich
Apparently only 1 clock edge would seem to affect the functioning of a ff but if you look into the internals you will see that both positive and negative edges affect its operation so to say that a flip flop is triggered only by a single edge is inaccurate. One clock edge permits data to be put in the master while isolating it from the slave the other edge closes the input gates and permits transfer from data to the slave ... the same operations apply to the slave latch. The advantage of having a 1 clock cycle delay is if you cascade flip flops you can transfer data previously stored in one flip flop to the next one while writing new data in the former one in a single clock cycle... each one is set one by one in resonse to successive enabling transitions which would otherwise be impossible if designed differently.
lemonjuice
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