Question about folded cascode

"Offset" is proportional to W*L (area).

"Fudging" size ratios to eliminate offset is _not_ a good idea ;-)

...Jim Thompson

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| James E.Thompson, P.E.                           |    mens     |
| Analog Innovations, Inc.                         |     et      |
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What did you do with M15, compared to M6 and M7, to be sure that M3 and M4 have enough voltage to operate? M15, M6 and M7 are all running at 1mA, and if these are identical transistors, there won't be anything left for M3 and M4.

Are you talking about offset in terms of monte-carlo analysis, or do you have offset using the same model for each flavor of transistor? That is, in real life, mismatch in M6/M7 causes input referred offset. Higher transconductance in the long tail pair reduces this effect.

If you running this in spice and getting offset without introducing variance in components, your circuit is probably not biased correctly. You need to insure that under all conditions, VDS exceeds VDSAT.

I never used a folded cascode in real life, but the thing simulates like a champ.

This is my circuit: i have used ideal voltage sources instead current mirrors to reduce problems...

My circuit satisfy all requirements except the great offset voltage (this is represented in picture). In this picture i have rapresented Vsd-Vsg+|Vp| of Q5 and Q7: so when this value is greater than zero, transistor is in saturation region. Vbias2 is obtained from condition on Voutmax: when Vout=Voutmax(=1.7V) Q5 and Q7 are in saturation region and have the same Vsd (it is equal to intersection point in second picture). Q5 is in saturation region for a greater range then Q7, so i don't think that is the problem (i am new in this field, so i'm not totally sure). If Is5 increases, gain became smaller If Vbias2 decreases, offset change slowly but Voutmax is greatly reduced If W of cascode load is reduced, offset is reduced but Voutmin also As i have said, the only way to obtain good results is W7 greater than W6, but i'm not totally sure on this solution...can you help me? Thanks for the help

Is what you are calling "offset" the output of -1.262V ??

That's what it should be ;-)

...Jim Thompson

--
| James E.Thompson, P.E.                           |    mens     |
| Analog Innovations, Inc.                         |     et      |
| Analog/Mixed-Signal ASIC\'s and Discrete Systems  |    manus    |
| Phoenix, Arizona  85048    Skype: Contacts Only  |             |
| Voice:(480)460-2350  Fax: Available upon request |  Brass Rat  |
| E-mail Icon at http://www.analog-innovations.com |    1962     |

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Yes, it's very big but i'm not able to eliminate it...any suggestion?

I don't understand

Examine your circuit from the point of view of SYMMETRY.

By symmetry the output MUST BE -1.262V when the inputs are at equal potentials, is that not so?

Keep in mind that you are dealing with perfectly matched devices. In the real world there should be enough gain to overcome that... high-Z load.

Otherwise think cascoding so that there is a ground reference on the left side of the cascode structure.

...Jim Thompson

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| James E.Thompson, P.E.                           |    mens     |
| Analog Innovations, Inc.                         |     et      |
| Analog/Mixed-Signal ASIC\'s and Discrete Systems  |    manus    |
| Phoenix, Arizona  85048    Skype: Contacts Only  |             |
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I'm confused... if In+=3DIn-, q4-6-8-10 have the same bias (current and voltage) values of q5-7-9-11.... If I4,I1,Vbias1 and Vbias2 are fixed (by other requirements) =3D>I6=3DI4- I1, Vsd4 and Vsd6 are known,so Vout is what it shoud be:it is what you mean?

Vout=3D-1.262V can be called offset or not?I've studied offset as output voltage when In+=3DIn-=3D0...is this right? An offset like this, can be accepted or not? (i'm really new in this field)

Thanks for the suggestion...i'll try to implement it

Vout is what it should be... it matches the V(D) of the adjacent diode-connected NMOS.

...Jim Thompson

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| James E.Thompson, P.E.                           |    mens     |
| Analog Innovations, Inc.                         |     et      |
| Analog/Mixed-Signal ASIC\'s and Discrete Systems  |    manus    |
| Phoenix, Arizona  85048    Skype: Contacts Only  |             |
| Voice:(480)460-2350  Fax: Available upon request |  Brass Rat  |
| E-mail Icon at http://www.analog-innovations.com |    1962     |

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Connect the positive input to ground and the negative input to the output of the op amp. The output voltage will be the offset.

You are making this much more complicated than it really is.